PIC16F84A-20I/P Microchip Technology, PIC16F84A-20I/P Datasheet - Page 655

• Manufacturer Part Number: PIC16F84A-20I/P
• Description: IC MCU FLASH 1KX14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-20I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 64 B
• Height: 3.3 mm
• Length: 22.86 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F84A - BOARD DAUGHTER ICEPIC3DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A.1
1997 Microchip Technology Inc.
Initiating and Terminating Data Transfer
During times of no data transfer (idle time), both the clock line (SCL) and the data line (SDA) are
pulled high through the external pull-up resistors. The START and STOP conditions determine
the start and stop of data transmission. The START condition is defined as a high to low transition
of the SDA when the SCL is high. The STOP condition is defined as a low to high transition of
the SDA when the SCL is high.
generates these conditions for starting and terminating data transfer. Due to the definition of the
START and STOP conditions, when data is being transmitted, the SDA line can only change state
when the SCL line is low.
Figure A-1:
Table A-1:
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization
Term
Start and Stop Conditions
I
2
C Bus Terminology
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock and terminates
the transfer.
The device addressed by a master.
More than one master device in a system. These masters can attempt to
control the bus at the same time without corrupting the message.
Procedure that ensures that only one of the master devices will control the
bus. This ensure that the transfer data does not get corrupted.
Procedure where the clock signals of two or more devices are synchro-
nized.
SDA
SCL
Condition
Start
S
Figure A-1
Change
Allowed
of Data
shows the START and STOP conditions. The master
Description
Change
Allowed
of Data
Condition
Appendix A
Stop
P
DS31034A-page 34-3
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