PIC16C63A-20I/SS Microchip Technology, PIC16C63A-20I/SS Datasheet - Page 135
![IC MCU OTP 4KX14 PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16C63A-20I/SS
Manufacturer Part Number
PIC16C63A-20I/SS
Description
IC MCU OTP 4KX14 PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C63A-04SP.pdf
(184 pages)
2.PIC16C63A-04SP.pdf
(7 pages)
3.PIC16C63A-04SP.pdf
(10 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C63A-20I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- PIC16C63A-04SP PDF datasheet
- PIC16C63A-04SP PDF datasheet #2
- PIC16C63A-04SP PDF datasheet #3
- PIC16C63A-04SP PDF datasheet #4
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TABLE 16-13: I
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
Param.
* These parameters are characterized but not tested.
2000 Microchip Technology Inc.
100*
101*
102*
103*
106*
107*
109*
110*
No.
90*
91*
92*
2: A fast mode (400 kHz) I
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
requirement Tsu:DAT
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line T
dard mode I
T
T
T
T
T
T
SU
SU
T
SU
HD
HD
Sym
T
T
HIGH
LOW
T
Cb
T
BUF
AA
:
:
:
:
R
:
F
STA
DAT
STO
DAT
STA
2
C BUS DATA REQUIREMENTS
2
Bus capacitive loading
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
START condition
setup time
START condition
hold time
Data input hold time 100 kHz mode
Data input setup
time
STOP condition
setup time
Output valid from
clock
Bus free time
C bus specification) before the SCL line is released.
250 ns must then be met. This will automatically be the case if the device does not
2
Characteristic
C bus device can be used in a standard mode (100 kHz) I
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
PIC16C63A/65B/73B/74B
R
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the stan-
20 + 0.1Cb
20 + 0.1Cb
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for Repeated
START condition
After this period the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
2
C bus system, but the
DS30605C-page 135
Conditions
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