PIC16C63A-20I/SS Microchip Technology, PIC16C63A-20I/SS Datasheet - Page 27
![IC MCU OTP 4KX14 PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16C63A-20I/SS
Manufacturer Part Number
PIC16C63A-20I/SS
Description
IC MCU OTP 4KX14 PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C63A-04SP.pdf
(184 pages)
2.PIC16C63A-04SP.pdf
(7 pages)
3.PIC16C63A-04SP.pdf
(10 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C63A-20I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- PIC16C63A-04SP PDF datasheet
- PIC16C63A-04SP PDF datasheet #2
- PIC16C63A-04SP PDF datasheet #3
- PIC16C63A-04SP PDF datasheet #4
- Current page: 27 of 184
- Download datasheet (3Mb)
4.5
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-4:
Note 1: For register file map detail, see Figure 4-2.
2000 Microchip Technology Inc.
RP1:RP0
bank select
0
2: Shaded portions are not implemented; maintain the IRP and RP1 bits clear.
Indirect Addressing, INDF and
FSR Registers
location select
6
Direct Addressing
Data
Memory
DIRECT/INDIRECT ADDRESSING
from opcode
00h
7Fh
Bank 0
00
0
80h
FFh
Bank 1
01
PIC16C63A/65B/73B/74B
100h
17Fh
Bank 2
10
not used
EXAMPLE 4-2:
NEXT
CONTINUE
Note:
180h
1FFh
Bank 3
11
Maintain the IRP and RP1 bits clear.
IRP
movlw
movwf
clrf
incf
btfss
goto
:
0
bank select
7
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
Indirect Addressing
INDIRECT ADDRESSING
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
FSR register
DS30605C-page 27
location select
0
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