PIC16C63A-20I/SS Microchip Technology, PIC16C63A-20I/SS Datasheet - Page 15
![IC MCU OTP 4KX14 PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16C63A-20I/SS
Manufacturer Part Number
PIC16C63A-20I/SS
Description
IC MCU OTP 4KX14 PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C63A-04SP.pdf
(184 pages)
2.PIC16C63A-04SP.pdf
(7 pages)
3.PIC16C63A-04SP.pdf
(10 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C63A-20I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- PIC16C63A-04SP PDF datasheet
- PIC16C63A-04SP PDF datasheet #2
- PIC16C63A-04SP PDF datasheet #3
- PIC16C63A-04SP PDF datasheet #4
- Current page: 15 of 184
- Download datasheet (3Mb)
4.0
4.1
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this data sheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
Accessing a location above 0FFFh will cause a wrap-
around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 4-1:
2000 Microchip Technology Inc.
CALL,RETURN
RETFIE,RETLW
MEMORY ORGANIZATION
Program Memory Organization
On-chip Program
Memory (Page 0)
On-chip Program
Memory (Page 1)
Interrupt Vector
Stack Level 1
Stack Level 8
RESET Vector
PC<12:0>
PIC16C63A/65B/73B/74B
PROGRAM MEMORY MAP
AND STACK
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
PIC16C63A/65B/73B/74B
4.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
RP1:RP0 (STATUS<6:5>)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All implemented banks contain SFRs. Frequently used
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
4.2.1
The register file can be accessed either directly, or indi-
rectly, through the File Select Register (FSR)
(Section 4.5).
= 00
= 01
= 10
= 11
Note:
Bank0
Bank1
Bank2
Bank3
Data Memory Organization
Maintain the IRP and RP1 bits clear in
these devices.
GENERAL PURPOSE REGISTER
FILE
DS30605C-page 15
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