PIC24FJ128GA008-I/PT Microchip Technology, PIC24FJ128GA008-I/PT Datasheet

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... Microchip corporate web site (www.microchip.com). TABLE 1: SILICON DEVREV VALUES Part Number PIC24FJ128GA010 PIC24FJ96GA010 PIC24FJ64GA010 PIC24FJ128GA008 PIC24FJ96GA008 PIC24FJ64GA008 PIC24FJ128GA006 PIC24FJ96GA006 PIC24FJ64GA006 Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. They are shown in hexadecimal in the format “DEVID DEVREV”. ...

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... Insertion of spurious data with auto-baud reception. Failure to exit Doze mode on certain traps. Single glitch on initialization under certain conditions. Device may not wake when convert on INT0 trigger is selected. Frame Sync unavailable in Master mode under certain conditions. (1) Affected Revisions © 2009 Microchip Technology Inc. ...

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... I C Slave mode 55. Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Issue Summary Module in Slave mode may ignore SS pin and receive data anyway. Two-Speed Start-up failure when IESO is enabled. ...

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... Incorrect status bit timing. Pin toggling error on alarm repeat. Spec change for V and Framed SPI modes not supported. Interrupt flag set early in Enhanced Buffer mode under certain conditions. General code protection disables bootloader functionality. (1) Affected Revisions © 2009 Microchip Technology Inc. ...

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... Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 3. Module: UART With the parity option enabled, a parity error, indicated with the PERR bit (UxSTA<3>) being set, may occur if the Baud Rate Generator contains an odd value. This affects both even and odd parity options ...

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... Stop events occur on the I sequence should be initiated only after a Start and a Stop event have been detected to ensure a bus collision can be detected. Affected Silicon Revisions and V -) and 6 LSbs for REF REF and multi-master 2 C multi-master network bus. A Start © 2009 Microchip Technology Inc. ...

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... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 12. Module: CPU A DISI instruction may be ignored if the command is executed in the same instruction cycle as when the DISICNT register decrements to zero. For example DISI #5 instruction is performed, the DISICNT will decrement to zero in six instruction cycles (5 instruction cycles for the DISI command plus 1 for the instruction execution) ...

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... Wait for the system to become Idle before setting the RCEN bit. Verify that the following bits are clear: ACKEN, RCEN, PEN, RSEN and SEN. Affected Silicon Revisions SECONDS 2 C peripheral may not 2 C slave transmit, refer © 2009 Microchip Technology Inc. ...

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... Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 22. Module: UART When UTXISEL<1:0> = 10, a UART interrupt flag should be set after one byte from the FIFO is transferred to the Transmit Shift Register (TSR). Instead, the interrupt flag may be set only after all bytes are transferred from the FIFO and the FIFO is empty ...

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... SCKx and SDOx waveforms are not affected. Work around Select the frame synchronization pulses to precede the first bit clock (SPIFE = 0). The frame pulses will output correctly as described in the product data sheet. Affected Silicon Revisions © 2009 Microchip Technology Inc. Use ...

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... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 33. Module: Core (Traps clock failure occurs when the device is in Idle mode, the oscillator failure trap does not vector to the Trap Service Routine. Instead, the device will simply wake-up from Idle mode and continue code execution if the Fail-Safe Clock Monitor (FSCM) is enabled ...

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... Subsequent PWM high and low times occur as expected. Work around If the current OCxRS register value is 0x0000, avoid writing a value of 0x0001 to OCxRS. Instead, write a value of 0x0002. In this case, how- ever, the duty cycle will be slightly different from the desired value. Affected Silicon Revisions © 2009 Microchip Technology Inc ...

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... BSET or BCLR instructions. or instructions with the .b modifier. Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 45. Module After the ACKSTAT bit is set, while receiving a NACK from the master or a slave, it may be cleared by the reception of a Start or Stop bit. Work around Store the value of the ACKSTAT bit immediately after receiving a NACK ...

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... POR/BOR and the first edge from the RTCC clock source. Work around Do not perform byte writes on ALCFGRPT, particularly the upper byte. Alternatively, wait until one period of the SOSC has completed before performing byte writes to ALCFGRPT. Affected Silicon Revisions © 2009 Microchip Technology Inc. ...

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... Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 54. Module (Master Mode) Under certain circumstances, a module operating in Master mode may Acknowledge its own com- mand addressed to a slave device. This happens when the following occurs: • 10-Bit Addressing mode is used (A10M = 1); ...

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... In this example, the RD1 pin functions as the SPI clock, SCK, which is configured as Idle low. Affected Silicon Revisions //wait for the transmission to complete //wait for the last clock to finish //write new data to the buffer C1 C2 © 2009 Microchip Technology Inc. ...

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... DO10 All I/O Pins Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 59. Module: I/O Pins The I/O pin output, V Table 3 below. ...

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... IVT and AIVT area of program space beyond the affected region. Map the addresses in the old vector tables to the new tables. These new tables can then be modified as needed to the Buffer mode actual addresses of the ISRs. Affected Silicon Revisions A2 A3 using the © 2009 Microchip Technology Inc. ...

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... The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39747D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS80471A-page 19 ...

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... This document replaces these errata documents: • “PIC24FJ128GA010 Family Rev. A2 Silicon Errata” (DS80275) • “PIC24FJ128GA010 Family Rev. A3 Silicon Errata” (DS80295) • “PIC24FJ128GA010 Family Rev. A4 Silicon Errata” (DS80330) • “PIC24FJ128GA010 Family Rev. C1 Silicon Errata” (DS80422) © 2009 Microchip Technology Inc has been ...

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