PIC24FJ128GA008-I/PT Microchip Technology, PIC24FJ128GA008-I/PT Datasheet - Page 5

• Manufacturer Part Number: PIC24FJ128GA008-I/PT
• Description: IC PIC MCU FLASH 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA008-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011, DV164033, MA240011, AC164127
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 69
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC24
• Maximum Speed: 16 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: Core
2. Module: I
© 2009 Microchip Technology Inc.
Note:
With Doze mode enabled, DOZEN (CLKDIV<11>)
set and the CPU Peripheral Clock Ratio Select bits
(CLKDIV<14:12>) configured to any value except
‘000’, writes to SFR locations can not be
performed.
Work around
Disable Doze mode or select 1:1 CPU peripheral
clock ratio before modifying stated SFR locations,
or avoid writing stated locations while Doze mode
is enabled and a CPU peripheral clock ratio other
than 1:1 is selected. Configure the device prior to
entering Doze mode and use the mode only to
monitor applications activity.
Affected Silicon Revisions
Writing to I2CxTRN during a Start bit transmission
generates a write collision, indicated by the
IWCOL (I2CxSTAT<7>) bit being set. In this state,
additional writes to the I2CxTRN register should
be blocked. However, in this condition, the
I2CxTRN register can be written, although
transmissions will not occur until the IWCOL bit is
cleared in software.
Work around
After each write to the I2CxTRN register, read the
IWCOL bit to ensure a collision has not occurred.
If the IWCOL bit is set, it must be cleared in
software and I2CxTRN must be rewritten.
Affected Silicon Revisions
A2
A2
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (C2).
A3
A3
X
2
C™
A4
A4
X
C1
C1
C2
C2
PIC24FJ128GA010 FAMILY
3. Module: UART
4. Module: Resets
With the parity option enabled, a parity error,
indicated with the PERR bit (UxSTA<3>) being set,
may occur if the Baud Rate Generator contains an
odd value. This affects both even and odd parity
options.
Work around
Load the Baud Rate Generator register, UxBRG,
with an even value or disable the peripheral’s par-
ity option by loading either ‘00’ or ‘11’ into the
Parity and Data Selection bits, PDSEL<1:0>
(UxMODE<2:1>).
Affected Silicon Revisions
After an oscillator has stopped, with the Fail-Safe
Clock Monitor enabled and the FCKSM<1:0> Con-
figuration bits (Flash Configuration Word 2<7:6>)
programmed to ‘00’, the system clock source is
forced to FRC. After which, the system clock source
may not be changed in software by modifying the
New
(OSCCON<10:8>), unless a device Reset occurs.
Work around
Upon detecting an oscillator failure, determined by
reading
(OSCCON<3>), as set, execute a RESET instruc-
tion prior to selecting a new system clock source
using the NOSC bits.
Affected Silicon Revisions
A2
A2
X
X
Oscillator
A3
A3
X
the
A4
A4
X
Clock
Selection
C1
C1
Fail
C2
C2
bits,
Detect
DS80471A-page 5
NOSC<2:0>
bit,
CF