PIC24FJ128GA008-I/PT Microchip Technology, PIC24FJ128GA008-I/PT Datasheet - Page 6

• Manufacturer Part Number: PIC24FJ128GA008-I/PT
• Description: IC PIC MCU FLASH 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA008-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011, DV164033, MA240011, AC164127
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 69
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC24
• Maximum Speed: 16 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ128GA010 FAMILY
5. Module: Timers
6. Module: SPI (Enhanced Mode)
7. Module: JTAG (Programming)
DS80471A-page 6
With Timer2 and Timer3 configured in 32-bit mode
by setting T2CON<3>, a Special Event Trigger to
start an A/D conversion may not occur when the
most significant word of the Period register, PR3,
is ‘0’.
Work around
Either write PR3 to a non-zero value or configure
Timer3 for 16-bit operation when generating a
Special
conversions.
Affected Silicon Revisions
The Enhanced SPI modes, selected by setting the
Enhanced
(SPIxCON2<0>), are not available.
Work around
Use Standard SPI mode by clearing the SPI
Enhanced Buffer Enable bit, SPIBEN.
Affected Silicon Revisions
The current JTAG programming implementation is
not compatible with third party programmers using
SVF (Serial Vector Format) description language.
JTAG boundary scan is supported by third party
JTAG solutions and is not affected.
Work around
The user can program devices with In-Circuit
Serial Programming™. JTAG programming can be
accomplished using custom JTAG software. The
current implementation may not be supported in
future PIC24F revisions. JTAG boundary scan is
supported.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
Event
Buffer
A4
A4
A4
X
X
Trigger
C1
C1
C1
Enable
C2
C2
C2
for
bit,
periodic
SPIBEN
A/D
8. Module: A/D
9. Module: I
Gain error may be as high as 5 LSbs for external
references (V
internal reference (AV
Work around
Determine gain error from a known reference
voltage and compensate the A/D result in
software.
Affected Silicon Revisions
The I
ing a Restart or Stop sequence. When this occurs,
the Master Bus Collision Detect bit, BCL
(I2CxSTAT<10>), may not set. The BCL bit will
indicate a bus collision, if it occurs, during a Start
sequence. This issue only affects I
networks.
Work around
To use the device in an I
each master device must detect when Start and
Stop events occur on the I
sequence should be initiated only after a Start and
a Stop event have been detected to ensure a bus
collision can be detected.
Affected Silicon Revisions
A2
A2
X
X
2
C module may not detect a bus collision dur-
A3
A3
X
2
C
REF
A4
A4
X
+ and V
© 2009 Microchip Technology Inc.
C1
C1
DD
2
and AV
C multi-master network,
C2
C2
REF
-) and 6 LSbs for
2
SS
C bus. A Start
2
).
C multi-master