AT89C5122D-PSTUM Atmel, AT89C5122D-PSTUM Datasheet - Page 159
AT89C5122D-PSTUM
Manufacturer Part Number
AT89C5122D-PSTUM
Description
IC 8051 MCU FLASH 32K 64QFN
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C5122D-PSTUM.pdf
(208 pages)
Specifications of AT89C5122D-PSTUM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFN
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- Current page: 159 of 208
- Download datasheet (3Mb)
INT1 Interrupt Vector
INT1 Input
RXD Input
CPRES Input
4202F–SCR–07/2008
The INT1 interrupt is multiplexed with the following three inputs:
•
•
•
The setting configurations for each input is detailed below.
This interrupt input is active under the following conditions :
•
•
•
The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is
cleared when interrupt is processed.
A second vector interrupt input is the reception of a character. UART Rx input can gen-
erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA
must also be set.
Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on
P3.0/RXD input.
The third input is the detection of a level change on CPRES input (P1.2). This input can
generate an interrupt if enabled with PRESEN (ISEL.1) , EX1 (IE0.2) and EA (IE0.7)
Bits.
This detection is done according to the level selected with Bit CPLEV (ISEL.7).
Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are
met. This Bit must be cleared by software.
INT1 : Standard 8051 interrupt input
RXD : Received data on UART
CPRES: Insertion or remove of the main card
It must be enabled by OEEN Bit (ISEL Register)
It can be active on a level or falling edge following IT1 Bit (TCON Register) status
If level triggering selection is set, the active level 0 or 1 can be selected with OELEV
Bit (ISEL Register)
AT83R5122, AT8xC5122/23
159
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