PIC32MX420F032H-40I/MR Microchip Technology, PIC32MX420F032H-40I/MR Datasheet - Page 25
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PIC32MX420F032H-40I/MR
Manufacturer Part Number
PIC32MX420F032H-40I/MR
Description
IC PIC MCU FLASH 32KX32 64-QFN
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX420F032H-40I/MR
Core Size
32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
MIPS32® M4K™
Speed
40MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC32
Ram Memory Size
8KB
Cpu Speed
40MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, JTAG, SPI, TWI, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Details
14.0
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
14.1
Memory verify is performed using the GET_CRC
command (see Table 16-3) as shown below.
FIGURE 14-1:
The following steps are required to verify memory using
the PE:
1.
2.
3.
4.
Verify that valCkSum matches the checksum of the
copy held in the programmer’s buffer.
14.2
Reading from Flash memory is performed by executing
a series of read accesses from the Fastdata register.
Table 19-4 shows the EJTAG programming details,
including the address and opcode data for performing
processor access operations.
© 2010 Microchip Technology Inc.
Note:
XferFastData (GET_CRC).
XferFastData (start_Address).
XferFastData (length).
valCkSum = XferFastData (32’h0x0).
VERIFY DEVICE MEMORY
Verifying Memory with the PE
Verifying Memory without the PE
Because
include the device code protection bit,
code memory should be verified immedi-
ately after writing (if code protection is
enabled). This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit has
been cleared.
Issue Verify Command
Receive Response
VERIFYING MEMORY
WITH THE PE
the
Configuration
registers
FIGURE 14-2:
The following steps are required to verify memory:
1.
2.
3.
4.
TABLE 14-1:
Opcode
Step 1: Initialize some constants.
3c04bf80
Step 2: Read memory Location.
3c08<ADDR>
3508<ADDR>
Step 3: Write to Fastdata location.
8d090000
ae690000
Step 4: Read data from Fastdata register
Step 5: Repeat Steps 2-4 until all configuration
XferInstruction
Repeat Step 1 until the last instruction is
transferred to the CPU.
Verify that valRead matches the copy held in the
programmer’s buffer.
Repeat Steps 1-3 for each memory location.
No
0xFF200000.
locations are read.
Instruction
lui $s3, 0xFF20
lui $t0,<FLASH_WORD_ADDR(31:16)>
ori $t0,<FLASH_WORD_ADDR(15:0)>
lw $t1, 0($t0)
sw $t1, 0($s3)
VERIFY DEVICE OPCODES
Read Memory Location
(opcode).
VERIFYING MEMORY
WITHOUT THE PE
Verify Location
Done
PIC32MX
DS61145G-page 25