PIC32MX420F032H-40I/MR Microchip Technology, PIC32MX420F032H-40I/MR Datasheet - Page 58
![IC PIC MCU FLASH 32KX32 64-QFN](/photos/12/13/121325/c04-149_mr_sml.jpg)
PIC32MX420F032H-40I/MR
Manufacturer Part Number
PIC32MX420F032H-40I/MR
Description
IC PIC MCU FLASH 32KX32 64-QFN
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX420F032H-40I/MR
Core Size
32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
MIPS32® M4K™
Speed
40MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC32
Ram Memory Size
8KB
Cpu Speed
40MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, JTAG, SPI, TWI, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Details
PIC32MX
19.2.5
The width of the Fastdata register is 1 bit. During a fast
data access, the Fastdata register is written and read
(i.e., a bit is shifted in and a bit is shifted out). During a
fast data access, the Fastdata register value shifted in
specifies whether the fast data access should be com-
pleted or not. The value shifted out is a flag that indi-
cates whether the fast data access was successful or
not (if completion was requested). The FASTDATA
access is used for efficient block transfers between the
DMSEG segment (on the probe) and target memory
(on the processor). An “upload” is defined as a
sequence that the processor loads from target memory
and stores to the DMSEG segment. A “download” is a
sequence of processor loads from the DMSEG seg-
ment and stores to target memory. The “Fastdata area”
specifies the legal range of DMSEG segment
addresses (0xFF20.0000-0xFF20.000F) that can be
used for uploads and downloads. The Data and Fast-
data registers (selected with the FASTDATA instruction)
allow efficient completion of pending Fastdata area
accesses.
During Fastdata uploads and downloads, the proces-
sor will stall on accesses to the Fastdata area. The
PrAcc (processor access pending bit) will be 1 indicat-
ing the probe is required to complete the access. Both
upload and download accesses are attempted by shift-
ing in a zero SPrAcc value (to request access comple-
tion) and shifting out SPrAcc to see if the attempt will be
successful (i.e., there was an access pending and a
legal Fastdata area address was used).
Downloads will also shift in the data to be used to
satisfy the load from the DMSEG segment Fastdata
area, while uploads will shift out the data being stored
to the DMSEG segment Fastdata area.
As noted above, two conditions must be true for the
Fastdata access to succeed. These are:
• PrAcc must be 1 (i.e., there must be a pending
• The Fastdata operation must use a valid Fastdata
DS61145G-page 58
processor access).
area address in the DMSEG segment
(0xFF20.0000 to 0xFF20.000F).
ETAP_FAST DATA COMMAND
© 2010 Microchip Technology Inc.