PIC16F876A-I/SP Microchip Technology, PIC16F876A-I/SP Datasheet - Page 229

• Manufacturer Part Number: PIC16F876A-I/SP
• Description: IC MCU FLASH 8KX14 EE 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876A-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16F876AI/SP

Timing Parameter Symbology .......................................... 181
TMR0 Register ................................................................... 19
TMR1CS Bit ....................................................................... 57
TMR1H Register ................................................................ 19
TMR1L Register ................................................................. 19
TMR1ON Bit ....................................................................... 57
TMR2 Register ................................................................... 19
TMR2ON Bit ....................................................................... 61
TMRO Register .................................................................. 21
TOUTPS0 Bit ..................................................................... 61
TOUTPS1 Bit ..................................................................... 61
TOUTPS2 Bit ..................................................................... 61
TOUTPS3 Bit ..................................................................... 61
TRISA Register .................................................................. 20
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I
I
I
I
I
I
I
I
I
I
Parallel Slave Port (PIC16F874A/877A Only) .......... 187
Parallel Slave Port (PSP) Read ................................. 52
Parallel Slave Port (PSP) Write ................................. 52
Repeat Start Condition ............................................. 100
Reset, Watchdog Timer, Start-up Timer
Slave Mode General Call Address Sequence
Slave Synchronization ............................................... 77
Slow Rise Time (MCLR Tied to V
SPI Master Mode (CKE = 0, SMP = 0) .................... 188
SPI Master Mode (CKE = 1, SMP = 1) .................... 188
SPI Mode (Master Mode) ........................................... 76
SPI Mode (Slave Mode with CKE = 0) ....................... 78
SPI Mode (Slave Mode with CKE = 1) ....................... 78
SPI Slave Mode (CKE = 0) ...................................... 189
SPI Slave Mode (CKE = 1) ...................................... 189
Stop Condition Receive or Transmit Mode .............. 104
Synchronous Reception
Synchronous Transmission ...................................... 122
Synchronous Transmission (Through TXEN) .......... 122
Time-out Sequence on Power-up
Time-out Sequence on Power-up (MCLR Tied
Timer0 and Timer1 External Clock .......................... 185
USART Synchronous Receive
USART Synchronous Transmission
Wake-up from Sleep via Interrupt ............................ 157
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 191
C Bus Start/Stop Bits ............................................. 190
C Master Mode (Reception, 7-bit Address) ........... 103
C Master Mode (Transmission,
C Slave Mode (Transmission, 10-bit Address) ........ 89
C Slave Mode (Transmission, 7-bit Address) .......... 87
C Slave Mode with SEN = 1 (Reception,
C Slave Mode with SEN = 0 (Reception,
C Slave Mode with SEN = 0 (Reception,
C Slave Mode with SEN = 1 (Reception,
7 or 10-bit Address) ......................................... 102
10-bit Address) ................................................... 93
10-bit Address) ................................................... 88
7-bit Address) ..................................................... 86
7-bit Address) ..................................................... 92
and Power-up Timer ........................................ 184
(7 or 10-bit Address Mode) ................................ 94
RC Network) .................................................... 152
(Master Mode, SREN) ...................................... 124
(MCLR Not Tied to V
Case 1 .............................................................. 152
Case 2 .............................................................. 152
to V
(Master/Slave) .................................................. 193
(Master/Slave) .................................................. 193
DD
via RC Network) ................................... 151
DD
)
DD
via
TRISB Register .................................................................. 20
TRISC Register .................................................................. 20
TRISD Register .................................................................. 20
TRISE Register .................................................................. 20
TXREG Register ................................................................ 19
TXSTA Register ................................................................. 20
U
USART ............................................................................. 111
USART Synchronous Receive Requirements ................. 193
V
V
Voltage Reference Specifications .................................... 180
V
DD
SS
Pin ...........................................................................9, 13
Pin ...........................................................................9, 13
IBF Bit ........................................................................ 50
IBOV Bit ..................................................................... 50
OBF Bit ...................................................................... 50
PSPMODE Bit ........................................... 48, 49, 50, 51
BRGH Bit ................................................................. 111
CSRC Bit ................................................................. 111
SYNC Bit ................................................................. 111
TRMT Bit .................................................................. 111
TX9 Bit ..................................................................... 111
TX9D Bit .................................................................. 111
TXEN Bit .................................................................. 111
Address Detect Enable (ADDEN Bit) ....................... 112
Asynchronous Mode ................................................ 115
Asynchronous Receive (9-bit Mode) ........................ 119
Asynchronous Receive with Address Detect.
Asynchronous Receiver ........................................... 117
Asynchronous Reception ......................................... 118
Asynchronous Transmitter ....................................... 115
Baud Rate Generator (BRG) ................................... 113
Clock Source Select (CSRC Bit) .............................. 111
Continuous Receive Enable (CREN Bit) .................. 112
Framing Error (FERR Bit) ........................................ 112
Mode Select (SYNC Bit) .......................................... 111
Overrun Error (OERR Bit) ........................................ 112
Receive Data, 9th Bit (RX9D Bit) ............................. 112
Receive Enable, 9-bit (RX9 Bit) ............................... 112
Serial Port Enable (SPEN Bit) ..........................111, 112
Single Receive Enable (SREN Bit) .......................... 112
Synchronous Master Mode ...................................... 121
Synchronous Master Reception ............................... 123
Synchronous Master Transmission ......................... 121
Synchronous Slave Mode ........................................ 124
Synchronous Slave Reception ................................. 125
Synchronous Slave Transmit ................................... 124
Transmit Data, 9th Bit (TX9D) ................................. 111
Transmit Enable (TXEN Bit) .................................... 111
Transmit Enable, 9-bit (TX9 Bit) .............................. 111
Transmit Shift Register Status (TRMT Bit) .............. 111
See Asynchronous Receive (9-bit Mode).
Baud Rate Formula ......................................... 113
Baud Rates, Asynchronous Mode
Baud Rates, Asynchronous Mode
High Baud Rate Select (BRGH Bit) ................. 111
Sampling .......................................................... 113
(BRGH = 0) .............................................. 114
(BRGH = 1) .............................................. 114
PIC16F87XA
DS39582B-page 227