PIC16F84A-20I/SS Microchip Technology, PIC16F84A-20I/SS Datasheet - Page 268
![IC MCU FLASH 1KX14 EE 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F84A-20I/SS
Manufacturer Part Number
PIC16F84A-20I/SS
Description
IC MCU FLASH 1KX14 EE 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84A-20I/SS
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
20MHz
No. Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
13
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Data Rom Size
64 B
Height
1.75 mm
Length
7.2 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4 V
Width
5.3 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPI3-DB16F84A - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F84A-20I/SS
Manufacturer:
MICROCHIP
Quantity:
2 560
Part Number:
PIC16F84A-20I/SS
Manufacturer:
MIC
Quantity:
20 000
- Current page: 268 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
16.4.1.1
DS31016A-page 16-18
Addressing
Once the SSP module has been enabled, it waits for a START condition to occur. Following the
START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled
with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to
the value of the SSPADD register. The address is compared on the falling edge of the eighth clock
(SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events
occur:
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be received by the slave. The five Most
Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. The R/W bit
(SSPSTAT<2>) must specify a write, so the slave device will receive the second address byte.
For a 10-bit address the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two
MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9
for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Table 16-2: Data Transfer Received Byte Actions
Note:Shaded cells show the conditions where the user software did not properly clear the overflow con-
Note:
transfer is received
Status bits as data
The SSPSR register value is loaded into the SSPBUF register on the falling edge of the
eight SCL pulse.
The buffer full bit, BF, is set on the falling edge of the eight SCL pulse.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF, is set (interrupt is generated if enabled) - on the falling edge
of the ninth SCL pulse.
Receive first (high) byte of Address (the SSPIF, BF, and UA (SSPSTAT<1>) bits are set).
Update the SSPADD register with second (low) byte of Address (clears the UA bit and
releases the SCL line).
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
Receive second (low) byte of Address (the SSPIF, BF, and UA bits are set).
Update the SSPADD register with the first (high) byte of Address. This will clear the UA bit
and release the SCL line.
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
Receive repeated START condition.
Receive first (high) byte of Address (the SSPIF and BF bits are set).
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
BF
0
1
1
0
dition
Following the RESTART condition (step 7) in 10-bit mode, the user only needs to
match the first 7-bit address. The user does not update the SSPADD for the second
half of the address.
SSPOV
0
0
1
1
SSPSR
Yes
Yes
No
No
SSPBUF
Generate ACK
pulse
Yes
No
No
No
1997 Microchip Technology Inc.
(SSP Interrupt occurs
Set bit SSPIF
if enabled)
Yes
Yes
Yes
Yes
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