ATMEGA169V-1MC Atmel, ATMEGA169V-1MC Datasheet - Page 280
ATMEGA169V-1MC
Manufacturer Part Number
ATMEGA169V-1MC
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-1MC
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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ATmega169V/L
Table 128. Parallel Programming Characteristics, V
Notes:
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 127 on page 271, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface.
Figure 127. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the Serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
High:> 2 CPU clock cycles for f
Symbol
t
t
t
BVDV
OLDV
OHDZ
1.
2. t
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock
2. V
bits commands.
source to the XTAL1 pin.
t
WLRH_CE
WLRH
CC
Parameter
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
- 0.3V < AVCC < V
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock
is valid for the Chip Erase command.
MOSI
MISO
SCK
ck
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
(1)
AVCC
VCC
CC
+1.8 - 5.5V
= 5V ± 10% (Continued)
+1.8 - 5.5V
Min
0
(2)
Typ
ck
ck
>= 12 MHz
>= 12 MHz
Max
250
250
250
2514H–AVR–05/03
Units
ns
ns
ns
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