PIC24HJ128GP202-I/SP Microchip Technology, PIC24HJ128GP202-I/SP Datasheet - Page 263
![IC PIC MCU FLASH 128K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC24HJ128GP202-I/SP
Manufacturer Part Number
PIC24HJ128GP202-I/SP
Description
IC PIC MCU FLASH 128K 28DIP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
5.PIC24HJ32GP304-EML.pdf
(356 pages)
Specifications of PIC24HJ128GP202-I/SP
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit or 10-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
7
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- PIC24HJ32GP304-EML PDF datasheet #5
- Current page: 263 of 368
- Download datasheet (5Mb)
25.2
All
PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04
devices power their core digital logic at a nominal 2.5V.
This can create a conflict for designs that are required
to operate at a higher typical voltage, such as 3.3V. To
simplify
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and
PIC24HJ128GPX02/X04 family incorporate an on-chip
regulator that allows the device to run its core logic from
V
The regulator provides power to the core from the other
V
(less than 5 Ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
(Figure
regulator. The recommended value for the filter capac-
itor is provided in
“DC
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 25-1:
© 2011 Microchip Technology Inc.
DD
DD
Note:
.
Note 1: These are typical operating voltages. Refer
pins. When the regulator is enabled, a low-ESR
Characteristics”.
Tantalum
25-1). This helps to maintain the stability of the
10 µF
On-Chip Voltage Regulator
C
of
,
system
2: It is important for the low-ESR capacitor to
EFC
STARTUP
it takes approximately 20 μs for the on-chip
It is important for the low-ESR capacitor to
be placed as close as possible to the V
pin.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
to
“DC Characteristics”
ranges of V
be placed as close as possible to the V
pin.
3.3V
Table
Table 28-13
the
design,
is applied every time the device
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
28-13, located in
V
V
V
DD
DD
CAP
SS
PIC24H
STARTUP
and V
PIC24HJ32GP302/304,
all
located in
CAP
for the full operating
, code execution is
.
devices
(1)
Section 28.1
Section 28.1
CAP
in
CAP
CAP
the
pin
25.3
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the
regulated supply voltage V
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
Brown-out Reset (BOR)
CAP
. The main purpose of
DS70293E-page 263
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