PIC18F4331-I/PT Microchip Technology, PIC18F4331-I/PT Datasheet - Page 23

• Manufacturer Part Number: PIC18F4331-I/PT
• Description: IC PIC MCU FLASH 4KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4331-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F4331-I/PTR; PIC18F4331-I/PTR

4.3
A configuration address may be read and output on
SDATA via the 4-bit command, ‘1001’. Configuration
data is read and written in a byte-wise fashion, so it is
not necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 for implementation details of reading
configuration data.
4.4
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is read by loading
EEADR:EEADRH with the desired memory location
and initiating a memory read by appropriately configur-
ing the EECON1 register. The data will be loaded into
EEDATA, where it may be serially output on SDATA via
the 4-bit command, ‘0010’ (Shift Out Data Holding reg-
ister). A delay of P6 must be introduced after the falling
edge of the 8th SCLK of the operand to allow SDATA to
transition from an input to an output. During this time,
SCLK must be held low (see Figure 4-4).
The command sequence to read a single byte of data
is shown in Table 4-2.
 2010 Microchip Technology Inc.
Verify Configuration Bits
Read Data EEPROM Memory
PIC18F2331/2431/4331/4431
FIGURE 4-3:
No
Move to TABLAT
Shift Out Data
READ DATA EEPROM
FLOW
Address
Read
Done
Done
Start
Byte
Set
?
Yes
DS30500B-page 23