PIC18F4331-I/PT Microchip Technology, PIC18F4331-I/PT Datasheet - Page 166
![IC PIC MCU FLASH 4KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4331-I/PT
Manufacturer Part Number
PIC18F4331-I/PT
Description
IC PIC MCU FLASH 4KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18F4331-I/PT
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
9 bit
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Details
Other names
PIC18F4331-I/PTR
PIC18F4331-I/PTR
PIC18F4331-I/PTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4331-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F4331-EP PDF datasheet #8
- Current page: 166 of 400
- Download datasheet (7Mb)
PIC18F2331/2431/4331/4431
When in Counter mode, the counter must be
configured
(T5SYNC = 0). When configured in Asynchronous
mode, the IC module will not work properly.
FIGURE 16-4:
DS39616C-page 164
Note 1: Input
Note 1: TMR5 is a synchronous time base input to the input capture, prescaler = 1:1. It increments on Q1 rising edge.
TMR5
CAP1 Pin
CAP1BUF
TMR5 Reset
Instruction
Execution
2: When the Input Capture mode is changed
3: During IC mode changes, the prescaler
(1)
2: IC1 is configured in Edge Capture mode (CAP1M3:CAP1M0 = 0010) with the time base reset upon edge capture
3: TMR5 value is latched by CAP1BUF on T
4: TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used with the input capture, it is active
5: TMR5 Reset pulse is disabled by clearing the CAP1REN bit (e.g., BCF CAP1CON, CAP1REN).
(2)
(cleared) when the input capture module
is disabled (CAPxM = 0000).
without first disabling the module and
entering the new Input Capture mode, a
false interrupt (or Special Event Trigger
on IC1) may be generated. The user
should either: (1) disable the input
capture before entering another mode, or
(2) disable IC interrupts to avoid false
interrupts during IC mode changes.
count will not be cleared, therefore the
first capture in the new IC mode may be
from the non-zero prescaler.
(3)
(CAP1REN = 1) and no noise filter.
the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated
with the incremented value of the time base on the next T
4 when Reset occurs).
immediately after the time base value is captured.
as
(4)
OSC
MOVWF CAP1CON
the
capture
Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
EDGE CAPTURE MODE TIMING
0012
synchronous
prescalers
0013
ABCD
counter
0014
are
reset
CY
only
Preliminary
. In the event that a write to TMR5 coincides with an input capture event,
0015
0000
CY
16.1.1
In this mode, the value of the time base is captured
either on every rising edge, every falling edge, every
4th rising edge, or every 16th rising edge. The edge
present on the input capture pin (CAP1, CAP2 or
CAP3) is sampled by the synchronizing latch. The
signal is used to load the Input Capture Buffer (ICxBUF
register) on the following Q1 clock (see Figure 16-4).
Consequently, Timer5 is either reset to ‘0’ (Q1
immediately following the capture event) or left free
running, depending on the setting of the Capture Reset
Enable bit, CAPxREN, in the CAPxCON register.
clock edge when the capture event takes place (see Note
Note:
0001
0016
BCF CAP1CON, CAP1REN
EDGE CAPTURE MODE
On the first capture edge following the
setting of the Input Capture mode (i.e.,
MOVWF CAP1CON), Timer5 contents are
always captured into the corresponding
Input Capture Buffer (i.e., CAPxBUF).
Timer5 can optionally be reset; however,
this is dependent on the setting of the
Capture Reset Enable bit, CAPxREN (see
Figure 16-4).
0002
© 2007 Microchip Technology Inc.
0000
0003
0001
0002
Note 5
0002
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