PIC18F4331-I/PT Microchip Technology, PIC18F4331-I/PT Datasheet - Page 67
![IC PIC MCU FLASH 4KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4331-I/PT
Manufacturer Part Number
PIC18F4331-I/PT
Description
IC PIC MCU FLASH 4KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18F4331-I/PT
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
9 bit
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Details
Other names
PIC18F4331-I/PTR
PIC18F4331-I/PTR
PIC18F4331-I/PTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4331-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F4331-EP PDF datasheet #8
- Current page: 67 of 400
- Download datasheet (7Mb)
5.8
Look-up tables are implemented two ways:
• Computed GOTO
• Table Reads
5.8.1
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-4.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, which returns the value 0xnn to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance, and
should be multiples of 2 (LSB = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-4:
5.8.2
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per pro-
gram word by using table reads and writes. The Table
Pointer (TBLPTR) specifies the byte address and the
Table Latch (TABLAT) contains the data that is read
from, or written to, program memory. Data is
transferred to/from program memory, one byte at a
time.
The table read/table write operation is discussed
further in Section 6.1 “Table Reads and Table
Writes”.
© 2007 Microchip Technology Inc.
ORG
TABLE
Look-up Tables
.
.
.
MOVFW
CALL
0xnn00
ADDWF
RETLW
RETLW
RETLW
TABLE READS/TABLE WRITES
COMPUTED GOTO
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET
TABLE
PCL
0xnn
0xnn
0xnn
PIC18F2331/2431/4331/4431
Preliminary
5.9
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 5-6
shows the data memory organization for the
PIC18F2331/2431/4331/4431 devices.
The data memory map is divided into as many as
16 banks that contain 256 bytes each. The lower 4 bits
of the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. The SFRs start at the last location of Bank
15 (FFFh) and extend to F60h. Any remaining space
beyond the SFRs in the bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ‘0’s.
The entire data memory may be accessed directly or
indirectly. Direct Addressing mode may require the use
of the BSR register. Indirect Addressing mode requires
the use of a File Select Register (FSRn) and a
corresponding Indirect File Operand (INDFn). Each
FSR holds a 12-bit address value that can be used to
access any location in the data memory map without
banking. See Section 5.12 “Indirect Addressing,
INDF and FSR Registers” for Indirect Addressing
details.
The instruction set and architecture allow operations
across all banks. This may be accomplished by Indirect
Addressing or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 5.10
“Access Bank” provides a detailed description of the
Access RAM.
5.9.1
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as GPR registers by all
instructions. The second half of Bank 15 (F60h to
FFFh) contains SFRs. All other banks of data memory
contain GPRs, starting with Bank 0.
Data Memory Organization
GENERAL PURPOSE REGISTER
FILE
DS39616C-page 65
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