DSPIC33FJ128GP204-I/ML Microchip Technology, DSPIC33FJ128GP204-I/ML Datasheet - Page 388
![IC DSPIC MCU/DSP 128K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128GP204-I/ML
Manufacturer Part Number
DSPIC33FJ128GP204-I/ML
Description
IC DSPIC MCU/DSP 128K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP204-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP204-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 388 of 402
- Download datasheet (3Mb)
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Revision C (May 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
• Changed all instances of V
The other changes are referenced by their respective
section in the following table.
TABLE A-2:
DS70292D-page 388
High-Performance, 16-Bit Digital
Signal Controllers
Section 1.0 “Device Overview”
Section 2.0 “Guidelines for Getting
Started with 16-Bit Digital Signal
Controllers”
Section 3.0 “CPU”
Section 4.0 “Memory Organization”
Section 5.0 “Flash Program
Memory”
Section 9.0 “Oscillator
Configuration”
OSCO to OSC2
V
CAP
to V
CAP
Section Name
/V
DDCORE
MAJOR SECTION UPDATES
DDCORE
and V
Updated all pin diagrams to denote the pin voltage tolerance (see “Pin
Diagrams”).
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which
references pin connections to V
Updated AV
Added Peripheral Pin Select (PPS) capability column to Pinout I/O
Descriptions (see Table 1-1).
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
Updated CPU Core Block Diagram with a connection from the DSP Engine
to the Y Data Bus (see Figure 3-1).
Vertically extended the X and Y Data Bus lines in the DSP Engine Block
Diagram (see Figure 3-3).
Updated Reset value for CORCON in the CPU Core Register Map (see
Table 4-1).
Updated the Reset values for IPC14 and IPC15 and removed the FLTA1IE
bit (IEC3) from the Interrupt Controller Register Map (see Table 4-4).
Updated bit locations for RPINR25 in the Peripheral Pin Select Input
Register Map (see Table 4-21).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-33).
Updated Section 5.3 “Programming Operations” with programming time
formula.
Updated the Oscillator System Diagram and added Note 2 (see Figure 9-1).
Added Note 1 and Note 2 to the OSCON register (see Register 9-1).
Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock
Divisor (CLKDIV) Register (see Register 9-2).
Added a paragraph regarding FRC accuracy at the end of Section 9.1.1
“System Clock Sources”.
Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”.
Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see
Register 9-4).
DDCORE
Preliminary
/
DD
in the PINOUT I/O Descriptions (see Table 1-1).
Update Description
SS
.
2009 Microchip Technology Inc.
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