DSPIC33FJ128GP204-I/ML Microchip Technology, DSPIC33FJ128GP204-I/ML Datasheet - Page 92
![IC DSPIC MCU/DSP 128K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128GP204-I/ML
Manufacturer Part Number
DSPIC33FJ128GP204-I/ML
Description
IC DSPIC MCU/DSP 128K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP204-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP204-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 92 of 402
- Download datasheet (3Mb)
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-1:
DS70292D-page 92
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 7-5
Note 1: For complete register details, see Register 3-1: “SR: CPU Status Register”.
R/W-0
R-0
OA
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
IPL<2:0>
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
R/W-0
R-0
OB
SR: CPU STATUS REGISTER
(2,3)
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
R/W-0
R/C-0
SA
R/C-0
R-0
RA
SB
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
R/W-0
OAB
R-0
N
(2)
R/W-0
R/C-0
SAB
OV
2009 Microchip Technology Inc.
R/W-0
R -0
DA
Z
R/W-0
R/W-0
DC
C
bit 8
bit 0
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