DSPIC33FJ128GP204-I/ML Microchip Technology, DSPIC33FJ128GP204-I/ML Datasheet - Page 69
![IC DSPIC MCU/DSP 128K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128GP204-I/ML
Manufacturer Part Number
DSPIC33FJ128GP204-I/ML
Description
IC DSPIC MCU/DSP 128K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP204-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP204-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 69 of 402
- Download datasheet (3Mb)
FIGURE 4-9:
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain
Program Counter
Table Operations
Program Space Visibility
(Remapping)
2: Table operations are not required to be word aligned. Table read operations are permitted
word alignment of data in the program and data spaces.
in the configuration memory space.
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
(2)
(1)
User/Configuration
(1)
Space Select
1/0
0
0
TBLPAG
8 bits
Preliminary
PSVPAG
8 bits
Select
Program Counter
1
24 bits
23 bits
23 bits
15 bits
16 bits
EA
EA
Byte Select
1/0
DS70292D-page 69
0
0
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