DSPIC33FJ128GP202-E/SO Microchip Technology, DSPIC33FJ128GP202-E/SO Datasheet - Page 217
![IC DSPIC MCU/DSP 128K 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
DSPIC33FJ128GP202-E/SO
Manufacturer Part Number
DSPIC33FJ128GP202-E/SO
Description
IC DSPIC MCU/DSP 128K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP202-E/SO
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 217 of 402
- Download datasheet (3Mb)
REGISTER 18-1:
2009 Microchip Technology Inc.
bit 4
bit 3
bit 2-1
bit 0
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
2: This feature is only available for the 16x BRG mode (BRGH = 0).
mation on enabling the UART module for receive or transmit operation.
URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
UxMODE: UART
x
MODE REGISTER (CONTINUED)
Preliminary
DS70292D-page 217
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