DSPIC33FJ64MC506-I/PT Microchip Technology, DSPIC33FJ64MC506-I/PT Datasheet - Page 160
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DSPIC33FJ64MC506-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506-I/PT
Description
IC DSPIC MCU/DSP 64K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.MA330013.pdf
(370 pages)
2.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
3.PIC24HJ12GP201-ISO.pdf
(84 pages)
4.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
5.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
6.DSPIC33FJ128MC506-IPT.pdf
(24 pages)
Specifications of DSPIC33FJ64MC506-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC506-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- MA330013 PDF datasheet
- DSPIC33FJ12GP201-ISO PDF datasheet #2
- PIC24HJ12GP201-ISO PDF datasheet #3
- DSPIC33FJ64MC506-IPT PDF datasheet #4
- DSPIC33FJ64MC506-IPT PDF datasheet #5
- DSPIC33FJ128MC506-IPT PDF datasheet #6
- Current page: 160 of 370
- Download datasheet (6Mb)
cumstances, however, where this is not practical. For
completely.
dsPIC33F
9.2.2
Idle mode has these features:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC also
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled.
• Any device Reset.
• A WDT time-out.
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAV instruction, or
the first instruction in the ISR.
9.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
9.3
Generally, changing clock speed and invoking one of the
power-saving modes are the preferred strategies for
reducing power consumption. There may be cir-
example, it may be necessary for an application to main-
tain uninterrupted synchronous communication, even
while it is doing nothing else. Reducing system clock
speed may introduce communication errors, while using
a power-saving mode may stop communications
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock contin-
ues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed, while the CPU clock speed is
reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70165E-page 158
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Peripheral Module Disable”).
remains active.
Doze Mode
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Preliminary
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>).
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
It is also possible to use Doze mode to selectively
reduce power consumption in event-driven applica-
tions. This allows clock-sensitive functions, such as
synchronous communications, to continue without
interruption while the CPU idles, waiting for something
to invoke an interrupt routine. Enabling the automatic
return to full-speed CPU operation on interrupts is
enabled by setting the ROI bit (CLKDIV<15>). By
default, interrupt events have no effect on Doze mode
operation.
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is now placed in Doze mode with a clock
frequency ratio of 1:4, the CAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
9.4
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled via the appropriate PMD
control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
A peripheral module is only enabled if both the associ-
ated bit in the PMD register is cleared and the peripheral
is supported by the specific dsPIC
peripheral is present in the device, it is enabled in the
PMD register by default.
Note:
Peripheral Module Disable
If a PMD bit is set, the corresponding mod-
ule is disabled after a delay of 1 instruction
cycle. Similarly, if a PMD bit is cleared, the
corresponding module is enabled after a
delay of 1 instruction cycle (assuming the
module control registers are already
configured to enable module operation).
There
© 2007 Microchip Technology Inc.
are
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