DSPIC33FJ64MC506-I/PT Microchip Technology, DSPIC33FJ64MC506-I/PT Datasheet - Page 202

• Manufacturer Part Number: DSPIC33FJ64MC506-I/PT
• Description: IC DSPIC MCU/DSP 64K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC506-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33F
16.7.2
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if QEISIDL (QEICON<13>) = 0.
This bit defaults to a logic ‘0’ upon executing POR. For
halting the timer module during the CPU Idle mode,
QEISIDL should be set to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally as if the CPU Idle mode had not been
entered.
16.8
The Quadrature Encoder Interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
• Detection of qualified index pulse or if CNTERR
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS3 register.
Enabling an interrupt is accomplished via the respec-
tive enable bit, QEIIE. The QEIIE bit is located in the
IEC3 register.
DS70165E-page 200
rollover/underflow
bit is set
Quadrature Encoder Interface
Interrupts
TIMER OPERATION DURING CPU
IDLE MODE
Preliminary
16.9
The QEI module has four user-accessible registers.
The registers are accessible in either Byte or Word
mode. These registers are:
• Control/Status Register (QEICON) – This register
• Digital Filter Control Register (DFLTCON) – This
• Position Count Register (POSCNT) – This loca-
• Maximum Count Register (MAXCNT) – The MAX-
allows control of the QEI operation and status
flags indicating the module state.
register allows control of the digital input filter
operation.
tion allows reading and writing of the 16-bit posi-
tion counter.
CNT register holds a value that will be compared
to the POSCNT counter in some operations.
Note:
Control and Status Registers
The
accesses, however, reading the register in
byte mode may result in partially updated
values in subsequent reads. Either use
Word mode reads/writes or ensure that
the counter is not counting during byte
operations.
POSCNT
© 2007 Microchip Technology Inc.
register
allows
byte