DSPIC33FJ64MC506A-I/PT Microchip Technology, DSPIC33FJ64MC506A-I/PT Datasheet - Page 133
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DSPIC33FJ64MC506A-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506A-I/PT
Description
IC DSPIC MCU/DSP 64K 64-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC506A-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
53
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
53
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Price
Company:
Part Number:
DSPIC33FJ64MC506A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
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7.4
7.4.1
To configure an interrupt source, do the following:
1.
2.
3.
4.
7.4.2
The method that is used to declare an Interrupt Service
Routine (ISR) and initialize the IVT with the correct vector
address will depend on the programming language (i.e.,
‘C’ or assembler) and the language development
toolsuite that is used to develop the application. In
general, the user must clear the interrupt flag in the
appropriate IFSx register for the source of interrupt that
the ISR handles. Otherwise, the ISR will be re-entered
immediately after exiting the routine. If the ISR is coded
in assembly language, it must be terminated using a
RETFIE instruction to unstack the saved PC value, SRL
value and old CPU priority level.
2009 Microchip Technology Inc.
Note:
Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
Interrupt Setup Procedures
INITIALIZATION
INTERRUPT SERVICE ROUTINE
At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to priority level 4.
dsPIC33FJXXXMCX06A/X08A/X10A
Preliminary
7.4.3
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4
All user interrupts can be disabled using the following
procedure:
1.
2.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (level 8-level 15)
cannot be disabled.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
TRAP SERVICE ROUTINE
INTERRUPT DISABLE
DS70594B-page 133
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