DSPIC33FJ64MC506A-I/PT Microchip Technology, DSPIC33FJ64MC506A-I/PT Datasheet - Page 68
![IC DSPIC MCU/DSP 64K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC33FJ64MC506A-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506A-I/PT
Description
IC DSPIC MCU/DSP 64K 64-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC506A-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
53
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
53
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC506A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC33FJ64MC506A-I/PTVAO
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dsPIC33FJXXXMCX06A/X08A/X10A
4.4.3
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than or greater
than the upper (for incrementing buffers) and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adjusted correctly.
4.5
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order;
thus, the only operand requiring reversal is the modifier.
4.5.1
Bit-Reversed Addressing mode is enabled when the
following conditions exist:
1.
2.
3.
DS70594B-page 68
Note:
The BWM bits (W register selection) in the
MODCON register are any value other than 15
(the
Bit-Reversed Addressing).
The BREN bit is set in the XBREV register.
The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
Bit-Reversed Addressing
stack
MODULO ADDRESSING
APPLICABILITY
The modulo corrected Effective Address is
written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (e.g.,
[W7+W2]) is used, Modulo Address
correction is performed but the contents of
the register remain unchanged.
BIT-REVERSED ADDRESSING
IMPLEMENTATION
cannot
be
accessed
using
Preliminary
If the length of a bit-reversed buffer is M = 2
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is only
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data
writes. It will not function for any other addressing
mode or for byte-sized data; normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
Note:
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo Addressing and Bit-Reversed
Addressing
together. In the event that the user attempts
to do so, Bit-Reversed Addressing will
assume priority for the X WAGU, and X
WAGU
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
Modulo
2009 Microchip Technology Inc.
should
Addressing
not
be
will
enabled
N
bytes,
be
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