PIC24HJ128GP504-I/PT Microchip Technology, PIC24HJ128GP504-I/PT Datasheet - Page 108
![IC PIC MCU FLASH 128K 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC24HJ128GP504-I/PT
Manufacturer Part Number
PIC24HJ128GP504-I/PT
Description
IC PIC MCU FLASH 128K 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
5.PIC24HJ32GP304-EML.pdf
(356 pages)
Specifications of PIC24HJ128GP504-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
7
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ128GP504-I/PT
Manufacturer:
MICROCHIP
Quantity:
3 400
Company:
Part Number:
PIC24HJ128GP504-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24HJ128GP504-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- PIC24HJ32GP304-EML PDF datasheet #5
- Current page: 108 of 356
- Download datasheet (6Mb)
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Eight DMA channels
• Register Indirect with Post-increment Addressing
• Register Indirect without Post-increment Address-
• Peripheral Indirect Addressing mode (peripheral
• CPU interrupt after half or full block transfer
FIGURE 8-1:
DS70293D-page 108
mode
ing mode
generates destination address)
complete
SRAM
Note:
SRAM X-Bus
CPU
CPU and DMA address buses are not shown for clarity.
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
PORT 1
DMA RAM
CPU Peripheral DS Bus
Peripheral
Non-DMA
PORT 2
Ready
DMA DS Bus
Preliminary
DMA Controller
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or Automatic (peripheral DMA
• One-Shot or Auto-Repeat block transfer modes
• Ping-Pong mode (automatic switch between two
• DMA request for each channel can be selected
• Debug support features
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
requests) transfer initiation
DPSRAM start addresses after each block trans-
fer complete)
from any supported interrupt source
Channels
DMA
Peripheral Indirect Address
Peripheral 1
CPU
Ready
DMA
© 2009 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA
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