DSPIC30F4011-30I/PT Microchip Technology, DSPIC30F4011-30I/PT Datasheet - Page 100

• Manufacturer Part Number: DSPIC30F4011-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401130IPT

dsPIC30F4011/4012
15.11 PWM Output and Polarity Control
There are three device configuration bits associated
with the PWM module that provide PWM output pin
control:
• HPOL configuration bit
• LPOL configuration bit
• PWMPIN configuration bit
These three bits in the FPORBOR configuration regis-
ter (see Section 21) work in conjunction with the three
PWM Enable bits (PWMEN<3:1>) located in the
PWMCON1 SFR. The configuration bits and PWM
Enable bits ensure that the PWM pins are in the correct
states after a device Reset occurs. The PWMPIN con-
figuration fuse allows the PWM module outputs to be
optionally enabled on a device Reset. If PWMPIN = 0,
the PWM outputs will be driven to their inactive states
at Reset. If PWMPIN = 1 (default), the PWM outputs
will be tri-stated. The HPOL bit specifies the polarity for
the PWMxH outputs, whereas the LPOL bit specifies
the polarity for the PWMxL outputs.
15.11.1
The PEN<3:1>H and PEN<3:1>L control bits in the
PWMCON1 SFR enable each high PWM output pin
and each low PWM output pin, respectively. If a partic-
ular PWM output pin not enabled, it is treated as a
general purpose I/O pin.
15.12 PWM FAULT Pin
There is one FAULT pin (FLTA) associated with the
PWM module. When asserted, these pins can option-
ally drive each of the PWM I/O pins to a defined state.
15.12.1
The FLTACON SFR has 3 control bits that determine
whether a particular pair of PWM I/O pins is to be
controlled by the FAULT input pin. To enable a
specific PWM I/O pin pair for FAULT overrides, the
corresponding bit should be set in the FLTACON
register.
If all enable bits are cleared in the FLTACON register,
then the corresponding FAULT input pin has no effect
on the PWM module and the pin may be used as a
general purpose interrupt or I/O pin.
DS70135C-page 98
Note:
OUTPUT PIN CONTROL
FAULT PIN ENABLE BITS
The FAULT pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the FLTACON register are cleared, then
the FAULT pin could be used as a general
purpose interrupt pin. The FAULT pin has
an interrupt vector, Interrupt Flag bit and
Interrupt Priority bits associated with it.
Preliminary
15.12.2
The FLTACON special function register has 6 bits that
determine the state of each PWM I/O pin when it is
overridden by a FAULT input. When these bits are
cleared, the PWM I/O pin is driven to the inactive state.
If the bit is set, the PWM I/O pin will be driven to the
active state. The active and inactive states are refer-
enced to the polarity defined for each PWM I/O pin
(HPOL and LPOL polarity control bits).
A special case exists when a PWM module I/O pair is
in the Complementary mode and both pins are pro-
grammed to be active on a FAULT condition. The
PWMxH pin always has priority in the Complementary
mode, so that both I/O pins cannot be driven active
simultaneously.
15.12.3
The FAULT input pin has two modes of operation:
• Latched Mode: When the FAULT pin is driven
• Cycle-by-Cycle Mode: When the FAULT input
The Operating mode for the FAULT input pin is
selected using the FLTAM control bit in the FLTACON
Special Function Register.
The FAULT pin can be controlled manually in software.
low, the PWM outputs will go to the states defined
in the FLTACON register. The PWM outputs will
remain in this state until the FAULT pin is driven
high and the corresponding interrupt flag has
been cleared in software. When both of these
actions have occurred, the PWM outputs will
return to normal operation at the beginning of the
next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the FAULT condi-
tion ends, the PWM module will wait until the
FAULT pin is no longer asserted, to restore the
outputs.
pin is driven low, the PWM outputs remain in the
defined FAULT states for as long as the FAULT
pin is held low. After the FAULT pin is driven high,
the PWM outputs return to normal operation at the
beginning of the following PWM cycle or
half-cycle boundary.
FAULT STATES
FAULT INPUT MODES
 2005 Microchip Technology Inc.