DSPIC30F4013-30I/P Microchip Technology, DSPIC30F4013-30I/P Datasheet - Page 101
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DSPIC30F4013-30I/P
Manufacturer Part Number
DSPIC30F4013-30I/P
Description
IC DSPIC MCU/DSP 48K 40DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F3014-30IPT.pdf
(228 pages)
3.DSPIC30F3014-30IPT.pdf
(16 pages)
4.DSPIC30F3014-30IPT.pdf
(6 pages)
5.DSPIC30F3014-30IPT.pdf
(14 pages)
6.DSPIC30F3014-30IPT.pdf
(20 pages)
7.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F4013-30I/P
Program Memory Type
FLASH
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
1024 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F4013-30IP
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Quantity
Price
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Manufacturer:
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15.3
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SSx pin
control enabled (SSEN = 1). When the SSx pin is low,
transmission and reception are enabled and the SDOx
pin is driven. When SSx pin goes high, the SDOx pin is
no longer driven. Also, the SPI module is resynchro-
nized, and all counters/control circuitry are reset.
Therefore, when the SSx pin is asserted low again,
transmission/reception begins at the MSb even if SSx
had been deasserted in the middle of a transmit/
receive.
15.4
During Sleep mode, the SPI module is shut down. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
2010 Microchip Technology Inc.
Slave Select Synchronization
SPI Operation During CPU Sleep
Mode
15.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
determines if the SPI module stops or continues on
Idle. If SPISIDL = 0, the module continues to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module stops when the CPU enters Idle mode.
dsPIC30F3014/4013
SPI Operation During CPU Idle
Mode
DS70138G-page 101