DSPIC30F4013-30I/P Microchip Technology, DSPIC30F4013-30I/P Datasheet - Page 114
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DSPIC30F4013-30I/P
Manufacturer Part Number
DSPIC30F4013-30I/P
Description
IC DSPIC MCU/DSP 48K 40DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F3014-30IPT.pdf
(228 pages)
3.DSPIC30F3014-30IPT.pdf
(16 pages)
4.DSPIC30F3014-30IPT.pdf
(6 pages)
5.DSPIC30F3014-30IPT.pdf
(14 pages)
6.DSPIC30F3014-30IPT.pdf
(20 pages)
7.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F4013-30I/P
Program Memory Type
FLASH
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
1024 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F4013-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
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DSPIC30F4013-30I/P
Manufacturer:
Microchip
Quantity:
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dsPIC30F3014/4013
17.4
17.4.1
The CAN bus module has 3 receive buffers. However,
one of the receive buffers is always committed to mon-
itoring the bus for incoming messages. This buffer is
called the Message Assembly Buffer (MAB). So there
are 2 receive buffers visible, denoted as RXB0 and
RXB1, that can essentially instantaneously receive a
complete message from the protocol engine.
All messages are assembled by the MAB and are trans-
ferred to the RXBn buffers only if the acceptance filter
criterion are met. When a message is received, the
RXnIF flag (CiINRF<0> or CiINRF<1>) is set. This bit
can only be set by the module when a message is
received. The bit is cleared by the CPU when it has com-
pleted processing the message in the buffer. If the
RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt
is generated when a message is received.
RXF0 and RXF1 filters with RXM0 mask are associated
with RXB0. The filters RXF2, RXF3, RXF4 and RXF5,
and the mask RXM1 are associated with RXB1.
17.4.2
The message acceptance filters and masks are used to
determine if a message in the message assembly buf-
fer should be loaded into either of the receive buffers.
Once a valid message has been received into the Mes-
sage Assembly Buffer (MAB), the identifier fields of the
message are compared to the filter values. If there is a
match, that message is loaded into the appropriate
receive buffer.
The acceptance filter looks at incoming messages for
the RXIDE bit (CiRXnSID<0>) to determine how to
compare the identifiers. If the RXIDE bit is clear, the
message is a standard frame and only filters with the
EXIDE bit (CiRXFnSID<0>) clear are compared. If the
RXIDE bit is set, the message is an extended frame
and only filters with the EXIDE bit set are compared.
17.4.3
The mask bits essentially determine which bits to apply
the filter to. If any mask bit is set to a zero, that bit is
automatically accepted regardless of the filter bit.
There are two programmable acceptance filter masks
associated with the receive buffers, one for each buffer.
DS70138G-page 114
Message Reception
RECEIVE BUFFERS
MESSAGE ACCEPTANCE FILTERS
MESSAGE ACCEPTANCE FILTER
MASKS
17.4.4
An overrun condition occurs when the Message
Assembly Buffer (MAB) has assembled a valid
received message, the message is accepted through
the acceptance filters, and when the receive buffer
associated with the filter has not been designated as
clear of the previous message.
The overrun error flag, RXnOVR (CiINTF<15> or
CiINTF<14>), and the ERRIF bit (CiINTF<5>) are set
and the message in the MAB is discarded.
If the DBEN bit is clear, RXB1 and RXB0 operate inde-
pendently. When this is the case, a message intended
for RXB0 is not diverted into RXB1 if RXB0 contains an
unread message, and the RX0OVR bit is set.
If the DBEN bit is set, the overrun for RXB0 is handled
differently. If a valid message is received for RXB0 and
RXFUL = 1 it indicates that RXB0 is full and
RXFUL = 0 indicates that RXB1 is empty, the message
for RXB0 is loaded into RXB1. An overrun error is not
generated for RXB0. If a valid message is received for
RXB0 and RXFUL = 1, indicates that both RXB0 and
RXB1 are full, the message is lost and an overrun is
indicated for RXB1.
17.4.5
The CAN module detects the following receive errors:
• Cyclic Redundancy Check (CRC) error
• Bit Stuffing error
• Invalid Message Receive Error
The receive error counter is incremented by one in
case one of these errors occur. The RXWAR bit
(CiINTF<9>) indicates that the receive error counter
has reached the CPU warning limit of 96 and an
interrupt is generated.
17.4.6
Receive interrupts can be divided into 3 major groups,
each including various conditions that generate
interrupts:
• Receive Interrupt:
• Wake-up Interrupt:
A message has been successfully received and
loaded into one of the receive buffers. This inter-
rupt is activated immediately after receiving the
End-of-Frame (EOF) field. Reading the RXnIF flag
indicates which receive buffer caused the
interrupt.
The CAN module has woken up from Disable
mode or the device has woken up from Sleep
mode.
RECEIVE OVERRUN
RECEIVE ERRORS
RECEIVE INTERRUPTS
2010 Microchip Technology Inc.