DSPIC30F4013-30I/P Microchip Technology, DSPIC30F4013-30I/P Datasheet - Page 44
![IC DSPIC MCU/DSP 48K 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
DSPIC30F4013-30I/P
Manufacturer Part Number
DSPIC30F4013-30I/P
Description
IC DSPIC MCU/DSP 48K 40DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F3014-30IPT.pdf
(228 pages)
3.DSPIC30F3014-30IPT.pdf
(16 pages)
4.DSPIC30F3014-30IPT.pdf
(6 pages)
5.DSPIC30F3014-30IPT.pdf
(14 pages)
6.DSPIC30F3014-30IPT.pdf
(20 pages)
7.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F4013-30I/P
Program Memory Type
FLASH
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
1024 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F4013-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4013-30I/P
Manufacturer:
Microchip
Quantity:
3 183
Part Number:
DSPIC30F4013-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F4013-30I/PT
Manufacturer:
MICROCHIP
Quantity:
1 600
Company:
Part Number:
DSPIC30F4013-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4013-30I/PT
Manufacturer:
MICR0CHIP
Quantity:
20 000
dsPIC30F3014/4013
5.4
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions or 96 bytes. Each panel consists of 128 rows or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multiple program memory panels, but the Table Pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a 32 address boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register.
32 TBLWTL
required to load the 32 instructions. If multiple panel
programming is required, the Table Pointer needs to be
changed and the next set of multiple write latches
written.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
The Flash program memory is readable, writable and
erasable during normal operation over the entire V
range.
DS70138G-page 44
RTSP Operation
and four
TBLWTH
instructions are
DD
5.5
The four SFRs used to read and write the program
Flash memory are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
5.5.1
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
the start of the programming cycle.
5.5.2
The NVMADR register is used to hold the lower two
bytes of the Effective Address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
5.5.3
The NVMADRU register is used to hold the upper byte
of the Effective Address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been executed.
5.5.4
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to
“Programming Operations”
Note:
Control Registers
NVMCON REGISTER
NVMADR REGISTER
NVMADRU REGISTER
NVMKEY REGISTER
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
2010 Microchip Technology Inc.
for further details.
Section 5.6