DSPIC33FJ32GS610-I/PT Microchip Technology, DSPIC33FJ32GS610-I/PT Datasheet - Page 342
![IC MCU/DSP 32KB FLASH 100TQFP](/photos/28/60/286070/100-tqfp-pt_sml.jpg)
DSPIC33FJ32GS610-I/PT
Manufacturer Part Number
DSPIC33FJ32GS610-I/PT
Description
IC MCU/DSP 32KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ32GS610-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Core Frequency
40MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
85
Flash Memory Size
32KB
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Most
double-word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction cycle(s)
executed as a NOP. Notable exceptions are the BRA
TABLE 25-1:
DS70591C-page 342
#text
(text)
[text]
{ }
<n:m>
.b
.d
.S
.w
Acc
AWB
bit4
C, DC, N, OV, Z
Expr
f
lit1
lit4
lit5
lit8
lit10
lit14
lit16
lit23
None
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
Wb
Wd
Wdo
Wm,Wn
instructions
Field
SYMBOLS USED IN OPCODE DESCRIPTIONS
are
a
single
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
Byte mode selection
Double-Word mode selection
Shadow register select
Word mode selection (default)
One of two accumulators {A, B}
Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
4-bit bit selection field (used in word-addressed instructions) {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address {0x0000...0x1FFF}
1-bit unsigned literal {0,1}
4-bit unsigned literal {0...15}
5-bit unsigned literal {0...31}
8-bit unsigned literal {0...255}
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal {0...16384}
16-bit unsigned literal {0...65535}
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
Field does not require an entry, can be blank
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
10-bit signed literal {-512...511}
16-bit signed literal {-32768...32767}
6-bit signed literal {-16...16}
Base W register {W0..W15}
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Dividend, Divisor Working register pair (Direct Addressing)
word.
Certain
Preliminary
(unconditional/computed branch), indirect CALL/GOTO,
all table reads and writes and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles. Certain instructions that involve
skipping over the subsequent instruction require either
two or three cycles if the skip is performed, depending
on whether the instruction being skipped is a single-word
or two-word instruction. Moreover, double-word moves
require two cycles.
Note:
Description
For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
2010 Microchip Technology Inc.
Reference
Manual”
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