ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 15
![MCU AVR 128K ISP FLASH 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA1284P-AU
Manufacturer Part Number
ATMEGA1284P-AU
Description
MCU AVR 128K ISP FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
Specifications of ATMEGA1284P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Rom Size
4 KB
Height
1.05 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
10.1 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
748
Part Number:
ATMEGA1284P-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 15 of 581
- Download datasheet (27Mb)
6.5.1
6.6
8272A–AVR–01/10
Instruction Execution Timing
SPH and SPL – Stack Pointer High and Stack pointer Low
Note:
Table 6-2.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 6-4 on page 15
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
1. Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
ATmega164A/ATmega164PA
ATmega324A/ATmega324PA
ATmega644A/ATmega644PA
shows the internal timing concept for the Register File. In a single clock cycle an ALU
ATmega1284/ATmega1284P
Stack Pointer size
The Parallel Instruction Fetches and Instruction Executions
R/W
SP7
15
R
–
7
0
1
clk
Device
CPU
shows the parallel instruction fetches and instruction executions enabled
SP6
R/W
14
R
–
6
0
1
SP5
R/W
CPU
13
R
–
5
0
1
T1
, directly generated from the selected clock source for the
SP12
0/0
SP4
R/W
R/W
12
4
1
(1)
T2
SP11
0/1
SP3
R/W
R/W
11
3
1
(1)
SP10
1/0
SP2
R/W
R/W
10
Stack Pointer size
2
1
(1)
SP[10:0]
SP[11:0]
SP[12:0]
SP[13:0]
T3
SP9
SP1
R/W
R/W
9
1
0
1
SP8
SP0
R/W
R/W
8
0
0
1
T4
SPH
SPL
15
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