ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 258
![MCU AVR 128K ISP FLASH 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA1284P-AU
Manufacturer Part Number
ATMEGA1284P-AU
Description
MCU AVR 128K ISP FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
Specifications of ATMEGA1284P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Rom Size
4 KB
Height
1.05 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
10.1 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
748
Part Number:
ATMEGA1284P-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 258 of 581
- Download datasheet (27Mb)
22.9.2
8272A–AVR–01/10
ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running Mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-
Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
Table 22-5.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x7A)
Read/Write
Initial Value
ADPS2
0
0
0
0
ADC Prescaler Selections
ADEN
R/W
7
0
ADSC
R/W
ADPS1
6
0
0
0
1
1
ADATE
R/W
5
0
ADIF
R/W
4
0
ADPS0
0
1
0
1
ADIE
R/W
3
0
ADPS2
R/W
2
0
ADPS1
R/W
Division Factor
1
0
2
2
4
8
ADPS0
R/W
0
0
ADCSRA
258
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