ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 186
![MCU AVR 128K ISP FLASH 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA1284P-AU
Manufacturer Part Number
ATMEGA1284P-AU
Description
MCU AVR 128K ISP FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
Specifications of ATMEGA1284P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Rom Size
4 KB
Height
1.05 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
10.1 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
748
Part Number:
ATMEGA1284P-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 186 of 581
- Download datasheet (27Mb)
18.9.2
8272A–AVR–01/10
Asynchronous Data Recovery
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples
denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).
Figure 18-5. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), to decide if a valid start bit is received. If two or more of these three samples have logical
high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-
ery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Speed mode.
the parity bit. Each of the samples is given a number that is equal to the state of the recovery
unit.
Figure 18-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 18-7 on page 187
of the start bit of the next frame.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
(U2X = 0)
(U2X = 1)
Sample
Sample
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
RxD
0
0
IDLE
0
1
1
1
1
shows the sampling of the stop bit and the earliest possible beginning
2
2
3
2
3
2
4
4
5
3
5
3
6
6
Figure 18-6
7
4
7
4
8
8
START
BIT n
9
5
9
5
10
10
shows the sampling of the data bits and
11
11
6
6
12
12
13
13
7
7
14
14
15
8
15
8
16
16
1
1
1
1
2
BIT 0
3
2
186
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