ATMEGA3290PV-10AU Atmel, ATMEGA3290PV-10AU Datasheet - Page 243

IC MCU 32K 4X40 LCD CTRL 100TQFP

ATMEGA3290PV-10AU

Manufacturer Part Number
ATMEGA3290PV-10AU
Description
IC MCU 32K 4X40 LCD CTRL 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA3290PV-10AU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA3290PV-8AU
ATMEGA3290PV-8AU

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23.5.3
8021G–AVR–03/11
LCDFRR – LCD Frame Rate Register
Table 23-3.
Note:
• Bit 7 – Reserved
This bit is reserved and will always read as zero.
• Bits 6:4 – LCDPS2:0: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in
23-4. Together they determine the prescaled LCD clock (clk
module.
Table 23-4.
Bit
(0xE6)
Read/Write
Initial Value
LCDPM3
LCDPS2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1. LCDPM3 is reserved and will always read as zero in ATmega329P.
LCDPM2
LCDPS1
LCD Port Mask (Values in bold are only available in ATmega3290P) (Continued)
LCD Prescaler Select
R
7
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
LCDPS2
R/W
LCDPM1
6
0
LCDPS0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
LCDPS1
R/W
5
0
LCDPM0
Output from
Prescaler
clk
clk
clk
clk
clk
clk
0
1
0
1
0
1
0
1
0
1
0
1
LCDPS0
LCD
LCD
LCD
R/W
LCD
LCD
LCD
4
0
/128
/256
/512
/16
/64
/N
I/O Port in Use as
R
Segment Driver
3
0
Applied Prescaled LCD Clock Frequency
SEG0:36
SEG0:38
SEG0:39
SEG0:20
SEG0:22
SEG0:23
SEG0:24
SEG0:26
SEG0:28
SEG0:30
SEG0:32
SEG0:34
when LCDCD2:0 = 0, Duty = 1/4, and
ATmega329P/3290P
LCDCD2
LCD_PS
R/W
2
0
Frame Rate = 64 Hz
), which is clocking the LCD
LCDCD1
R/W
130kHz
260kHz
1
0
8.1kHz
33kHz
66kHz
Maximum Number
LCDCD0
of Segments
R/W
0
0
21
23
24
25
27
29
31
33
35
37
39
40
LCDFRR
Table
243

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