DSPIC30F5011-20I/PT Microchip Technology, DSPIC30F5011-20I/PT Datasheet - Page 125
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DSPIC30F5011-20I/PT
Manufacturer Part Number
DSPIC30F5011-20I/PT
Description
IC DSPIC MCU/DSP 66K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F5011-20IPT.pdf
(220 pages)
2.DSPIC30F5011-20IPT.pdf
(16 pages)
3.DSPIC30F5011-20IPT.pdf
(6 pages)
4.DSPIC30F5011-20IPT.pdf
(14 pages)
5.DSPIC30F5011-20IPT.pdf
(26 pages)
Specifications of DSPIC30F5011-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
52
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F5011-20I/PTG
DSPIC30F501120/PT
DSPIC30F501120IPT
DSPIC30F501120IPT
DSPIC30F501120/PT
DSPIC30F501120IPT
DSPIC30F501120IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
18.6.2
The 20-bit AC-Link mode allows all bits in the data time
slots to be transmitted and received but does not main-
tain data alignment in the TXBUF and RXBUF
registers.
The 20-bit AC-Link mode functions similar to the Multi-
Channel mode of the DCI module, except for the duty
cycle of the frame synchronization signal. The AC-Link
frame synchronization signal should remain high for 16
CSCK cycles and should be low for the following
240 cycles.
The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
© 2011 Microchip Technology Inc.
20-BIT AC-LINK MODE
18.7
The DCI module is configured for I
a value of ‘01’ to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in the I
DCI module will generate frame synchronization sig-
nals with a 50% duty cycle. Each edge of the frame
synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
18.7.1
The WS and COFSG control bits are set to produce the
period for one half of an I
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
The BLEN bits must be set for the desired buffer length.
Setting BLEN<1:0> = 01 will produce a CPU interrupt,
once per I
18.7.2
As per the I
default, begin one CSCK cycle after a transition of the
WS signal. A ‘MSb left justified’ option can be selected
using the DJST control bit in the DCICON1 SFR.
If DJST = 1, the I
tified. The MSb of the data word will be presented on
the CSDO pin during the same CSCK cycle as the ris-
ing or falling edge of the COFS signal. The CSDO pin
is tri-stated after the data word has been sent.
dsPIC30F5011/5013
I
2
2
S Mode Operation
S frame.
2
I
LENGTH SELECTION
I
S specification, a data word transfer will, by
2
2
S FRAME AND DATA WORD
S DATA JUSTIFICATION
2
S data transfers will be MSb left jus-
2
S data frame. That is, the
2
DS70116J-page 125
S mode by writing
2
S mode, the