DSPIC30F5011-20I/PT Microchip Technology, DSPIC30F5011-20I/PT Datasheet - Page 213

• Manufacturer Part Number: DSPIC30F5011-20I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5011-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5011-20I/PTG; DSPIC30F501120/PT; DSPIC30F501120IPT; DSPIC30F501120IPT

I
I
I
I
I
I
Idle Current (I
In-Circuit Serial Programming (ICSP) ......................... 47, 137
Input Capture (CAPX) Timing Characteristics .................. 183
Input Capture Module ......................................................... 77
Input Capture Operation During Sleep and Idle Modes ...... 78
Input Capture Timing Requirements ................................. 183
Input Change Notification Module ....................................... 62
Instruction Addressing Modes............................................. 41
Instruction Set
© 2011 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 93
C 7-bit Slave Mode Operation .......................................... 93
C Master Mode Operation ................................................ 95
C Master Mode Support ................................................... 95
C Module .......................................................................... 91
S Mode Operation .......................................................... 125
Reception.................................................................... 94
Transmission............................................................... 94
Reception.................................................................... 93
Transmission............................................................... 93
Baud Rate Generator.................................................. 96
Clock Arbitration.......................................................... 96
Multi-Master Communication, Bus Collision and Bus Ar-
Reception.................................................................... 95
Transmission............................................................... 95
Addresses ................................................................... 93
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 95
Interrupts..................................................................... 95
IPMI Support ............................................................... 95
Operating Function Description .................................. 91
Operation During CPU Sleep and Idle Modes ............ 96
Pin Configuration ........................................................ 91
Programmer’s Model................................................... 91
Register Map............................................................... 97
Registers..................................................................... 91
Slope Control .............................................................. 95
Software Controlled Clock Stretching (STREN = 1).... 94
Various Modes ............................................................ 91
Data Justification....................................................... 125
Frame and Data Word Length Selection................... 125
Interrupts..................................................................... 78
Register Map............................................................... 79
CPU Idle Mode............................................................ 78
CPU Sleep Mode ........................................................ 78
dsPIC30F5011 Register Map (Bits 15-8) .................... 62
dsPIC30F5011 Register Map (Bits 7-0) ...................... 62
dsPIC30F5013 Register Map (Bits 15-8) .................... 62
dsPIC30F5013 Register Map (Bits 7-0) ...................... 62
File Register Instructions ............................................ 41
Fundamental Modes Supported.................................. 41
MAC Instructions......................................................... 42
MCU Instructions ........................................................ 41
Move and Accumulator Instructions............................ 42
Other Instructions........................................................ 42
Overview ................................................................... 154
Summary................................................................... 151
bitration ............................................................... 96
Master Mode ..................................................... 194
Slave Mode ....................................................... 196
Master Mode ..................................................... 195
Slave Mode ....................................................... 197
Master Mode ..................................................... 194
Slave Mode ....................................................... 196
IDLE
) ............................................................ 167
Internal Clock Timing Examples ....................................... 175
Internet Address ............................................................... 215
Interrupt Controller
Interrupt Priority .................................................................. 36
Interrupt Sequence ............................................................. 39
Interrupts ............................................................................ 35
L
Load Conditions................................................................ 173
Low Voltage Detect (LVD) ................................................ 147
Low-Voltage Detect Characteristics.................................. 170
LVDL Characteristics ........................................................ 171
M
Memory Organization ......................................................... 23
Microchip Internet Web Site.............................................. 215
Modes of Operation
Modulo Addressing ............................................................. 42
MPLAB ASM30 Assembler, Linker, Librarian ................... 160
MPLAB Integrated Development Environment Software.. 159
MPLAB PM3 Device Programmer .................................... 162
MPLAB REAL ICE In-Circuit Emulator System ................ 161
MPLINK Object Linker/MPLIB Object Librarian ................ 160
N
NVM
O
OC/PWM Module Timing Characteristics ......................... 185
Operating Current (I
Oscillator
Oscillator Selection ........................................................... 137
Oscillator Start-up Timer
Output Compare Interrupts ................................................. 84
Output Compare Module .................................................... 81
Output Compare Operation During CPU Idle Mode ........... 84
dsPIC30F5011/5013
Register Map .............................................................. 40
Traps .......................................................................... 37
Interrupt Stack Frame................................................. 39
Core Register Map ..................................................... 32
Disable...................................................................... 109
Initialization............................................................... 109
Listen All Messages.................................................. 109
Listen Only................................................................ 109
Loopback .................................................................. 109
Normal Operation ..................................................... 109
Applicability................................................................. 44
Incrementing Buffer Operation Example .................... 43
Start and End Address ............................................... 43
W Address Register Selection.................................... 43
Register Map .............................................................. 51
Configurations .......................................................... 140
Operating Modes (Table).......................................... 138
System Overview...................................................... 137
Timing Characteristics .............................................. 178
Timing Requirements ............................................... 179
Register Map .............................................................. 85
Timing Characteristics .............................................. 184
Timing Requirements ............................................... 184
Fail-Safe Clock Monitor .................................... 142
Fast RC (FRC).................................................. 141
Initial Clock Source Selection ........................... 140
Low Power RC (LPRC)..................................... 141
LP Oscillator Control......................................... 140
Phase Locked Loop (PLL) ................................ 141
Start-up Timer (OST)........................................ 140
DD
) .................................................... 165
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