PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 12

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX
6.3
Format:
Purpose:
Description (in sequence):
FIGURE 6-5:
FIGURE 6-6:
DS61145G-page 12
oData = XferData (iData)
To clock data to and from the register selected by the
command.
1.
2.
3.
4.
The TMS Header is clocked into the device to
select the Shift DR state.
The data is clocked in/out of the device on
TDI/TDO while holding signal TMS low.
The last MSb of the data is clocked in/out
while setting TMS high.
The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
TMS
TCK
TDO
TDI
XferData Pseudo Operation
PGC
PGD
TDI = iLSb
TDI = 0
TDI = 0
‘1’
Data (31’h12) + TMS = 0
TMS Header = 100
XferData 4-WIRE
XferData 2-WIRE (4-PHASE)
TMS = 0
TMS = 1
TMS = 1
‘0’
TDO = oLSb+1
TDO =
TDO =
TMS Footer =
...
‘0’
X
X
TMS Header =
TDI = 0
oLSb
10
iLSb
TDI = 0
Data (32’h12)
TDI = iMSb
Data (MSb) + TMS Footer = 1
TMS = 0
TMS = 0
100
TMS = 1
Restrictions:
Example:
None.
oData = XferData (32’h12)
Data (MSb)
TDO =
+ TMS = 1
TDO =
oMSb
iMSb
‘1’
X
X
TDO =
TDI = 0
X
‘1’
TMS Footer = 10
© 2010 Microchip Technology Inc.
TMS = 0
‘0’
TDO = oLSb