PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 23

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.0
Once a row of data has been downloaded into the
device’s SRAM, the programming sequence must be
initiated to write the block of data to Flash memory.
13.1
When using PE, the data is immediately written to the
Flash memory from the SRAM. No further action is
required.
13.2
Flash memory write operations are controlled by the
NVMCON register. Programming is performed by set-
ting NVMCON to select the type of write operation and
initiating the programming sequence by setting the WR
control bit NVMCON<15>.
FIGURE 13-1:
© 2010 Microchip Technology Inc.
INITIATING A FLASH ROW
WRITE
With the PE
Without the PE
Load Addresses in NVM Registers
Unprotect Control Registers
Unlock Flash Controller
Select Write Operation
Start Operation
INITIATING FLASH WRITE
WITHOUT THE PE
Done
The following steps are required to initiate a Flash
write:
1.
2.
TABLE 13-1:
Opcode
Step 1: Initialize some constants.
3c04bf80
3484f400
34054003
34068000
34074000
3c11aa99
36316655
3c125566
365299aa
3c13ff20
3c100000
Step 2: Set NVMADDR with the address of the Flash
3c08<ADDR>
3508<ADDR>
ac880020
Step 3: Set NVMSRCADDR with the physical source
3610<ADDR>
Step 4: Set up NVMCON for write operation and poll
ac850000
8C880000
31080800
1500fffd
00000000
Step 5: Unlock NVMCON and start write operation.
ac910010
ac920010
ac860008
Step 6: Repeatedly read the NVMCON register and
8c880000
01064024
1500fffd
00000000
XferInstruction (opcode).
Repeat Step 1 until the last instruction is
transferred to the CPU.
row to be programmed.
SRAM address.
LVDSTAT.
poll for WR bit to get cleared.
Instruction
lui a0,0xbf80
ori a0,a0,0xf400
ori a1,$0,0x4003
ori a2,$0,0x8000
ori a3,$0,0x4000
lui s1,0xaa99
ori s1,s1,0x6655
lui s2,0x5566
ori s2,s2,0x99aa
lui s3,0xff20
lui s0,0x0000
lui t0,<FLASH_ROW_ADDR(31:16)>
ori
sw
ori s0,s0,<RAM_ADDR(15:0)>
sw
delay (6 µs)
here1:
lw
andi t0,t0,0x0800
bne t0,$0,<here1>
nop
sw
sw
sw
here2:
lw
and t0,t0,a2
bne t0,$0,<here2>
nop
INITIATE FLASH ROW WRITE
OPCODES
t0,t0,<FLASH_ROW_ADDR(15:0)>
t0,32(a0)
a1,0(a0)
t0,0(a0)
s1,16(a0)
s2,16(a0)
a2,8(a0)
t0,0(a0)
PIC32MX
DS61145G-page 23