PIC18F6622-I/PT Microchip Technology, PIC18F6622-I/PT Datasheet - Page 136
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6622-I/PT
Manufacturer Part Number
PIC18F6622-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(446 pages)
3.PIC18F8627T-IPT.pdf
(44 pages)
4.PIC18F6527-IPT.pdf
(10 pages)
5.PIC18F8622-IPT.pdf
(448 pages)
Specifications of PIC18F6622-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
A/d Bit Size
10 bit
A/d Channels Available
12
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6622-I/PT
Manufacturer:
MICROCHI
Quantity:
3 000
Company:
Part Number:
PIC18F6622-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6622-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- PIC18F8627T-IPT PDF datasheet #3
- PIC18F6527-IPT PDF datasheet #4
- PIC18F8622-IPT PDF datasheet #5
- Current page: 136 of 446
- Download datasheet (7Mb)
PIC18F8722 FAMILY
10.6
External interrupts on the RB0/INT0, RB1/INT1, RB2/
INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into power-
managed modes. If the Global Interrupt Enable bit,
GIE, is set, the processor will branch to the interrupt
vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
EXAMPLE 10-1:
DS39646C-page 134
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTx Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
priority bit, TMR0IP (INTCON2<2>). See Section 12.0
module.
10.7
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt can
be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt
“Timer0 Module” for further details on the Timer0
10.8
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
10.9
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 10-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
© 2008 Microchip Technology Inc.
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