PIC18F448-I/PT Microchip Technology, PIC18F448-I/PT Datasheet - Page 237

• Manufacturer Part Number: PIC18F448-I/PT
• Description: IC PIC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F448-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 33
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Details

19.8
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2, as
necessary. There are two mechanisms used for
synchronization.
19.8.1
Hard synchronization is only done when there is a reces-
sive to dominant edge during a bus Idle condition, indi-
cating
synchronization, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge which
has occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of synchroniza-
tion, if a hard synchronization occurs, there will not be a
resynchronization within that bit time.
19.8.2
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 19-8) or subtracted from Phase Segment 2 (see
Figure 19-9). The SJW is programmable between 1 T
and 4 T
Clocking information will only be derived from reces-
sive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
FIGURE 19-8:
© 2006 Microchip Technology Inc.
Input
Signal
Bit
Time
Segments
T
Q
Q
the
Synchronization
.
HARD SYNCHRONIZATION
RESYNCHRONIZATION
start
Sync
of
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
Segment
a
Prop
message.
Nominal Bit Length
After
Segment 1
Phase
hard
Actual Bit Length
Q
The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in T
phase error is defined in magnitude of T
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
If the magnitude of the phase error is less than or equal
to the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
If the magnitude of the phase error is larger than the
synchronization jump width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the synchronization jump width.
If the magnitude of the phase error is larger than the
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the synchronization jump width.
19.8.3
• Only one synchronization within one bit time is
• An edge will be used for synchronization only if
• All other recessive to dominant edges, fulfilling
previous bit.
allowed.
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
rules 1 and 2, will be used for resynchronization
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
SJW
Sample Point
SYNCHRONIZATION RULES
PIC18FXX8
Segment 2
Phase
DS41159E-page 235
Q
as follows:
Q
. The