PIC18F4680-I/PT Microchip Technology, PIC18F4680-I/PT Datasheet - Page 478

IC MCU FLASH 32KX16 44TQFP

PIC18F4680-I/PT

Manufacturer Part Number
PIC18F4680-I/PT
Description
IC MCU FLASH 32KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4680-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
44
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 25 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4680-I/PT
Manufacturer:
LATTICE
Quantity:
2 667
Part Number:
PIC18F4680-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
PIC18F4680-I/PT
0
PIC18F2585/2680/4585/4680
SS .................................................................................... 187
SSPOV ............................................................................. 217
SSPOV Status Flag .......................................................... 217
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 64
Status Register ................................................................... 87
SUBFSR ........................................................................... 407
SUBFWB .......................................................................... 396
SUBLW ............................................................................ 397
SUBULNK ........................................................................ 407
SUBWF ............................................................................ 397
SUBWFB .......................................................................... 398
SWAPF ............................................................................ 398
T
Table Pointer Operations (table) ........................................ 98
Table Reads/Table Writes .................................................. 64
TBLRD ............................................................................. 399
TBLWT ............................................................................. 400
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 147
Timer1 .............................................................................. 151
Timer2 .............................................................................. 157
Timer3 .............................................................................. 159
DS39625B-page 476
Operation in Power Managed Modes ...................... 195
Serial Clock .............................................................. 187
Serial Data In ........................................................... 187
Serial Data Out ........................................................ 187
Slave Mode .............................................................. 193
Slave Select ............................................................. 187
Slave Select Synchronization .................................. 193
SPI Clock ................................................................. 192
Typical Connection .................................................. 191
R/W Bit ............................................................. 200, 201
Associated Registers ............................................... 149
Clock Source Edge Select (T0SE Bit) ...................... 148
Clock Source Select (T0CS Bit) ............................... 148
Operation ................................................................. 148
Overflow Interrupt .................................................... 149
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 148
16-Bit Read/Write Mode ........................................... 153
Associated Registers ............................................... 155
Interrupt .................................................................... 154
Operation ................................................................. 152
Oscillator .................................................................. 153
Resetting, Using a Special Event Trigger
Special Event Trigger (ECCP1) ............................... 174
Use as a Real-Time Clock ....................................... 154
Associated Registers ............................................... 158
Interrupt .................................................................... 158
Operation ................................................................. 157
Output ...................................................................... 158
PR2 Register .................................................... 169, 175
TMR2 to PR2 Match Interrupt .......................... 169, 175
16-Bit Read/Write Mode ........................................... 161
Associated Registers ............................................... 161
Operation ................................................................. 160
Oscillator .................................................. 151, 159, 161
Overflow Interrupt .................................... 151, 159, 161
Special Event Trigger (CCP) .................................... 161
TMR3H Register .............................................. 151, 159
TMR3L Register ............................................... 151, 159
Layout Considerations ..................................... 154
Output (CCP) ................................................... 154
Preliminary
Timing Diagrams
A/D Conversion ........................................................ 452
Acknowledge Sequence .......................................... 220
Asynchronous Reception ......................................... 239
Asynchronous Transmission .................................... 237
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 235
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 240
Baud Rate Generator with Clock Arbitration ............ 214
BRG Overflow Sequence ......................................... 235
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 438
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision for Transmit and Acknowledge .......... 221
Capture/Compare/PWM (CCP) ............................... 440
CLKO and I/O .......................................................... 437
Clock Synchronization ............................................. 207
Clock/Instruction Cycle .............................................. 65
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 442
Example SPI Master Mode (CKE = 1) ..................... 443
Example SPI Slave Mode (CKE = 0) ....................... 444
Example SPI Slave Mode (CKE = 1) ....................... 445
External Clock (All Modes Except PLL) ................... 435
Fail-Safe Clock Monitor ........................................... 356
First Start Bit Timing ................................................ 215
Full-Bridge PWM Output .......................................... 179
Half-Bridge PWM Output ......................................... 178
High/Low-Voltage Detect ......................................... 270
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4585/4680) ................... 441
Parallel Slave Port (PSP) Read ............................... 145
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 446
C Bus Start/Stop Bits ............................................ 446
C Master Mode (7 or 10-Bit Transmission) ........... 218
C Master Mode (7-Bit Reception) .......................... 219
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Transmission) .................... 205
C Slave Mode (7-Bit Reception, SEN = 0) ............ 202
C Slave Mode (7-Bit Reception, SEN = 1) ............ 208
C Slave Mode (7-Bit Transmission) ...................... 203
C Slave Mode General Call Address
(Back to Back) ................................................. 237
Normal Operation ............................................ 240
During Start Condition ..................................... 223
Condition (Case 1) ........................................... 224
Condition (Case 2) ........................................... 224
(SCL = 0) ......................................................... 223
(SDA Only) ...................................................... 222
(Case 1) ........................................................... 225
(Case 2) ........................................................... 225
(Master/Slave) ................................................. 450
(Master/Slave) ................................................. 450
SEN = 0) .......................................................... 204
SEN = 1) .......................................................... 209
Sequence (7 or 10-Bit Address Mode) ............ 210
2
2
C Bus Data ........................................ 448
C Bus Start/Stop Bits ........................ 448
 2004 Microchip Technology Inc.

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