PIC18LF6520-I/PT Microchip Technology, PIC18LF6520-I/PT Datasheet - Page 64

IC MCU FLASH 16KX16 EEPROM64TQFP

PIC18LF6520-I/PT

Manufacturer Part Number
PIC18LF6520-I/PT
Description
IC MCU FLASH 16KX16 EEPROM64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF6520-I/PT

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
52
Eeprom Memory Size
1024Byte
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
5
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Quantity
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PIC18F6520/8520/6620/8620/6720/8720
FIGURE 5-2:
5.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
5.2.1
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
Control bit CFGS determines if the access will be to the
configuration/calibration registers, or to program
memory/data EEPROM memory. When set, subse-
quent operations will operate on configuration regis-
ters, regardless of EEPGD (see Section 23.0 “Special
Features of the CPU”). When clear, memory selection
access is determined by EEPGD.
DS39609B-page 62
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
Control Registers
TBLPTRU
EECON1 AND EECON2 REGISTERS
TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in
Section 5.5 “Writing to Flash Program Memory”.
Table Pointer
TBLPTRH
TABLE WRITE OPERATION
(1)
TBLPTRL
Program Memory
(TBLPTR)
Instruction: TBLWT*
Holding Registers
Program Memory
The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR), due to Reset values of zero.
The WR control bit, initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation. The
inability to clear the WR bit in software prevents the
accidental or premature termination of a write
operation.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
 2004 Microchip Technology Inc.
Table Latch (8-bit)
TABLAT

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