PIC18F2682-I/SP Microchip Technology, PIC18F2682-I/SP Datasheet - Page 79
![IC PIC MCU FLASH 40KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2682-I/SP
Manufacturer Part Number
PIC18F2682-I/SP
Description
IC PIC MCU FLASH 40KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F2682-I/SP
Core Size
8-Bit
Program Memory Size
80KB (40K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1024Byte
Ram Memory Size
3.25KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Details
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 79 of 484
- Download datasheet (9Mb)
TABLE 5-2:
© 2009 Microchip Technology Inc.
STATUS
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
ECCPR1H
ECCPR1L
ECCP1CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1:
File Name
2:
3:
4:
5:
6:
7:
8:
9:
(9)
(9)
(9)
(9)
(9)
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
CAN bits have multiple functions depending on the selected mode of the CAN module.
This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
These registers and/or bits are available on PIC18F4682/4685 devices only.
(9)
(9)
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
Enhanced Capture/Compare/PWM Register 1 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
EPWM1M1 EPWM1M0
VDIRMAG
ECCPASE
TMR0ON
ABDOVF
CVREN
PRSEN
C2OUT
WCOL
IDLEN
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
T3ECCP1
T2OUTPS3 T2OUTPS2 T2OUTPS1
SBOREN
ACKSTAT
ECCPAS2
PDC6
SSPOV
CVROE
T08BIT
T1RUN
C1OUT
IRCF2
RCIDL
Bit 6
CKE
—
—
—
—
—
—
—
(3)
(2)
(9)
2
T1CKPS1
ECCPAS1
T3CKPS1
C™ Slave mode, MSSP Baud Rate Reload Register in I
EDC1B1
PDC5
SSPEN
ACKDT
VCFG1
ACQT2
DC1B1
IRCF1
IRVST
CVRR
C2INV
CHS3
T0CS
Bit 5
D/A
—
—
—
—
(3)
ECCPAS0
T1CKPS0
T3CKPS0
HLVDEN
EDC1B0
PDC4
ACKEN
CVRSS
PIC18F2682/2685/4682/4685
VCFG0
ACQT1
DC1B0
IRCF0
C1INV
CHS2
SCKP
T0SE
Bit 4
CKP
—
RI
N
P
(3)
T2OUTPS0
T1OSCEN
ECCP1M3
T3CCP1
CCP1M3
PSSAC1
HLVDL3
PDC3
SSPM3
PCFG3
ACQT0
BRG16
RCEN
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
OV
TO
—
S
(3)
(9)
ECCP1M2
TMR2ON
T1SYNC
CCP1M2
PSSAC0
T3SYNC
HLVDL2
PDC2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
Bit 2
R/W
PEN
CM2
PD
—
—
Z
(3)
2
C Master mode
PSSBD1
GO/DONE
ECCP1M1
T2CKPS1
TMR1CS
TMR3CS
CCP1M1
HLVDL1
PDC1
SSPM1
PCFG1
ADCS1
T0PS1
RSEN
CVR1
SCS1
WUE
POR
Bit 1
CM1
DC
UA
—
(3)
(3)
PSSBD0
ECCP1M0
T2CKPS0
SWDTEN
TMR1ON
TMR3ON
CCP1M0
HLVDL0
PDC0
SSPM0
ABDEN
PCFG0
ADCS0
T0PS0
ADON
CVR0
SCS0
BOR
Bit 0
SEN
CM0
BF
C
(3)
(3)
DS39761C-page 79
---x xxxx
0000 0000 52, 151
xxxx xxxx 52, 151
1111 1111 52, 151
0100 q000
0-00 0101 52, 267
0q-1 11q0 52, 129
xxxx xxxx 52, 157
0000 0000 52, 157
0000 0000 52, 153
1111 1111 52, 160
-000 0000 52, 157
-000 0000 52, 159
xxxx xxxx 52, 197
0000 0000 52, 197
0000 0000 52, 199
0000 0000 52, 200
0000 0000 52, 201
xxxx xxxx 52, 258
xxxx xxxx 52, 258
--00 0000 52, 249
--00 0qqq 52, 250
0-00 0000 53, 251
xxxx xxxx 53, 170
xxxx xxxx 53, 170
--00 0000 53, 165
xxxx xxxx 53, 169
xxxx xxxx 53, 169
0000 0000 53, 170
01-0 0-00 53, 232
0000 0000 53, 184
0000 0000 53, 185
0000 0000 53, 265
0000 0000 53, 259
xxxx xxxx 53, 163
xxxx xxxx 53, 163
0000 0000 53, 163
POR, BOR
--- ---0
Value on
on page:
Details
52, 356
52, 89
32, 52
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