PIC18F2685-I/SP Microchip Technology, PIC18F2685-I/SP Datasheet - Page 105

• Manufacturer Part Number: PIC18F2685-I/SP
• Description: IC PIC MCU FLASH 48KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2685-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is inter-
rupted by a MCLR Reset, or a WDT Time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
TABLE 6-2:
© 2009 Microchip Technology Inc.
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1:
PROGRAM_MEMORY
Name
Required
Sequence
These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CMIP
CMIF
CMIE
CFGS
Bit 6
—
(1)
(1)
(1)
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
bit 21
Bit 5
—
—
—
—
PIC18F2682/2685/4682/4685
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INT0IE
FREE
EEIP
EEIF
EEIE
Bit 4
WRERR
BCLIP
BCLIF
BCLIE
RBIE
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
Bit 3
6.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
6.6
See Section 24.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TMR0IF
HLVDIP
HLVDIE
HLVDIF
WREN
Bit 2
Flash Program Operation During
Code Protection
PROTECTION AGAINST
SPURIOUS WRITES
TMR3IP
TMR3IF
TMR3IE
INT0IF
Bit 1
WR
ECCP1IP
ECCP1IF
ECCP1IE
RBIF
Bit 0
RD
DS39761C-page 105
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(1)
Values on
Reset
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