PIC18F6621-I/PT Microchip Technology, PIC18F6621-I/PT Datasheet - Page 47

IC PIC MCU FLASH 32KX16 64TQFP

PIC18F6621-I/PT

Manufacturer Part Number
PIC18F6621-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F6621-I/PT

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1024Byte
Ram Memory Size
3.75KB
Cpu Speed
40MHz
No. Of Timers
5
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F6621-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6621-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F6621-I/PT
Quantity:
2 850
4.6
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
EXAMPLE 4-2:
4.7
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-6 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 4.4 “PCL,
PCLATH and PCLATU”).
The CALL and GOTO instructions have an absolute
program
instruction. Since instructions are always stored on
FIGURE 4-6:
 2005 Microchip Technology Inc.
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
4. BSF
5. Instruction @ address SUB_1
All instructions are single-cycle except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
Instruction Flow/Pipelining
Instructions in Program Memory
memory
PORTA, BIT3 (Forced NOP)
Instruction 1:
Instruction 2:
Instruction 3:
address
INSTRUCTION PIPELINE FLOW
INSTRUCTIONS IN PROGRAM MEMORY
Program Memory
Byte Locations
MOVLW
GOTO
MOVFF
Fetch 1
embedded
T
CY
0
055h
000006h
123h, 456h
Execute 1
Fetch 2
PIC18F6525/6621/8525/8621
into
T
CY
1
the
Execute 2
Fetch 3
LSB = 1
T
CY
EFh
C1h
0Fh
F0h
F4h
2
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
word boundaries, the data contained in the instruction
is a word address. The word address is written to
PC<20:1> which accesses the desired byte address in
program memory. Instruction #2 in Figure 4-6 shows
how the instruction “GOTO 000006h” is encoded in the
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The offset value stored in a branch instruction
represents the number of single-word instructions that
the PC will be offset by. Section 25.0 “Instruction Set
Summary” provides further details of the instruction
set.
Execute 3
Fetch 4
LSB = 0
T
CY
55h
03h
00h
23h
56h
3
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Word Address
00000Ah
00000Ch
00000Eh
000000h
000002h
000004h
000006h
000008h
000010h
000012h
000014h
T
CY
4
DS39612B-page 45
T
CY
5

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