PIC18F8585-I/PT Microchip Technology, PIC18F8585-I/PT Datasheet - Page 92

• Manufacturer Part Number: PIC18F8585-I/PT
• Description: IC PIC MCU FLASH 24KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8585-I/PT

• Core Size: 8-Bit
• Program Memory Size: 48KB (24K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.25KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3328 B
• Interface Type: I2C, SPI, AUSART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163015
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Details

PIC18F6585/8585/6680/8680
5.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
EXAMPLE 5-3:
DS30491C-page 90
READ_BLOCK
MODIFY_WORD
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load table pointer with address being erased.
Do the row erase procedure.
Load table pointer with address of first byte
being written.
Write the first 8 bytes into the holding registers
with auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
FLASH PROGRAM MEMORY WRITE
SEQUENCE
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
WRITING TO FLASH PROGRAM MEMORY
D’64
COUNTER
high(BUFFER_ADDR)
FSR0H
low(BUFFER_ADDR)
FSR0L
upper(CODE_ADDR)
TBLPTRU
high(CODE_ADDR)
TBLPTRH
low(CODE_ADDR)
TBLPTRL
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
high(DATA_ADDR)
FSR0H
low(DATA_ADDR)
FSR0L
low(NEW_DATA)
POSTINC0
high(NEW_DATA)
INDF0
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
; read into TABLAT, and inc
; get data
; store data
; done?
; repeat
; point to buffer
; update buffer word
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Execute a NOP.
14. Re-enable interrupts.
15. Repeat steps 6-14 seven times to write 64 bytes.
16. Verify the memory (table read).
This procedure will require about 40 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 5-3.
Note:
Disable interrupts.
Write 55h to EECON2.
5 ms using internal timer).
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the eight bytes
in the holding register.
 2004 Microchip Technology Inc.