AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 593
![IC MCU AVR32 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0128-ALUT
Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128-ALUT
Manufacturer:
Atmel
Quantity:
166
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30.8.2.19
Offset:
Register Name:
Access Type:
Reset Value:
• CH_EN: Channel Enable
Set this bit to enable this channel data transfer.
Clear this bit to disable the channel data transfer.
This may be used to start or resume any requested transfer.
This bit is cleared by hardware when the HSB source channel is disabled at end of dma buffer.
• LD_NXT_CH_DESC_EN: Load Next Channel Descriptor Enable
Set this bit to allow automatic next descriptor loading at the end of the channel transfer.
Clear this bit to disable this feature.
If set, the dma channel controller loads the next descriptor when the UDDMAX_STATUS.CH_EN bit is reset due to soft-
ware of hardware event (for example at the end of the current transfer).
• BUFF_CLOSE_IN_EN: Buffer Close Input Enable
Set this bit to automatically closed the current dma transfer at the end of the usb OUT data transfer (received short packet).
Clear this bit to disable this feature.
• DMAEND_EN: End of DMA Buffer Output Enable
Set this bit to properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (or a Zero Length Packet) will be sent to the usb line to properly closed the
usb transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
32058J–AVR32–04/11
BURST_LOCK
_EN
rwu
31
23
15
0
0
–
7
0
USB Device DMA Channel X Control Register (UDDMAX_CONTROL)
DESC_LD_
IRQ_EN
rwu
30
22
14
0
0
–
6
0
EOBUFF_
IRQ_EN
rwu
29
21
13
0
0
–
5
0
0x0318 + (X - 1) . 0x10
UDDMAX_CONTROL, X in [1..6]
Read/Write
0x00000000
EOT_IRQ_EN
rwu
28
20
12
CH_BYTE_LENGTH
CH_BYTE_LENGTH
0
0
–
4
0
rwu
rwu
DMAEND_EN
rwu
27
19
11
0
0
–
3
0
BUFF_CLOSE
_IN_EN
rwu
26
18
10
0
0
–
2
0
LD_NXT_CH_
DESC_EN
rwu
25
17
0
0
9
–
1
0
AT32UC3A
CH_EN
rwu
24
16
0
0
8
–
0
0
593
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