AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 642
![IC MCU AVR32 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0128-ALUT
Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128-ALUT
Manufacturer:
Atmel
Quantity:
166
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31.6.1.3
32058J–AVR32–04/11
Clock Control
Each channel can independently select an internal or external clock source for its counter:
• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,
• External clock signals: XC0, XC1 or XC2. The Peripherals Chapter details the connection of
This selection is made by the TCCLKS bits in the TC Channel Mode Register .
The selected clock can be inverted with the CLKI bit in CMR. This allows counting on the oppo-
site edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST
parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note:
Figure 31-2. Clock Selection
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See
• The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands
• The clock can also be started or stopped: a trigger (software, synchro, external or compare)
TIMER_CLOCK4, TIMER_CLOCK5. The Peripherals Chapter details the connection of these
clock sources.
these clock sources.
in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is
set to 1 in CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is
set to 1 in CMR. When disabled, the start or the stop actions have no effect: only a CLKEN
command in the Control Register can re-enable the clock. When the clock is enabled, the
CLKSTA bit is set in the Status Register.
always starts the clock. The clock can be stopped by an RB load event in Capture Mode
In all cases, if an external clock is used, the duration of each of its levels must be longer than the
master clock period. The external clock frequency must be at least 2.5 times lower than the mas-
ter clock
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Figure
31-3.
1
TCCLKS
BURST
CLKI
Selected
Clock
AT32UC3A
642
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