AT91M42800A-33AU Atmel, AT91M42800A-33AU Datasheet - Page 16

• Manufacturer Part Number: AT91M42800A-33AU
• Description: IC ARM7 MCU 144 LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M42800A-33AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: WDT
• Number Of I /o: 54
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB42
• Minimum Operating Temperature: - 40 C
• For Use With: AT91EB42 - KIT EVAL FOR ARM AT91M42800A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

8. Peripherals
8.1
8.2
16
Peripheral Registers
Peripheral Interrupt Control
AT91M42800A
The External Bus Interface also features the Early Read Protocol, configurable for all the
devices, which significantly reduces access time requirements on an external device.
The AT91M42800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus.
Peripheral registers are only word accessible. Byte and half-word accesses are not supported. If
a byte or a half-word access is attempted, the memory controller automatically masks the lowest
address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address
space).
The following registers are common to all peripherals:
Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward
compatibility. These bits read 0.
The Interrupt Control of each peripheral is controlled from the status register using the interrupt
mask. The status register bits are ANDed to their corresponding interrupt mask bits and the
result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt
Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes
it possible to enable or disable peripheral interrupt sources with a non-interruptible single
instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-time
and multi-tasking systems.
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte
• Control Register – Write-only register that triggers a command when a one is written to the
• Mode Register – read/write register that defines the configuration of the peripheral. Usually
• Data Registers – read and/or write register that enables the exchange of data between the
• Status Register – Read-only register that returns the status of the peripheral.
• Enable/Disable/Status Registers – shadow command registers. Writing a one in the Enable
Access Select mode) or two 8-bit devices in parallel that emulate a
16-bit memory (Byte Write Access mode).
corresponding position at the appropriate address. Writing a zero has no effect.
has a value of 0x0 after a reset.
processor and the peripheral.
Register sets the corresponding bit in the Status Register. Writing a one in the Disable
Register resets the corresponding bit and the result can be read in the Status Register.
Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit
manipulation, and enables modification of a register with a single non-interruptible
instruction, replacing the costly read-modify-write operation.
1779ES–ATARM–14-Apr-06